vlock_dis_cnt--;
else if (vlock_dis_cnt == 0) {
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
+ #if 0
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x4, 0, 3);
- amvecm_hiu_reg_write_bits(
+ #endif
+ if (IS_AUTO_MODE(vlock_mode))
+ amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x0, 0, 3);
}
u32 tmp_value, abs_val;
unsigned int ia, oa, abs_cnt;
unsigned int pre_m, new_m, tar_m, org_m;
+ static u32 m_diff_cnt, f_diff_cnt;
+ u32 mchange = 0;
/*vs_i*/
tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
return;
}
+ /*m*/
+ tmp_value = vlock_get_panel_pll_m();
+ if (vlock.dtdata->vlk_hwver < vlock_hw_ver2) {
+ abs_val = abs(((m_frac_diff_value >> 16) & 0xff) -
+ (pre_hiu_reg_m & 0xff));
+ if ((abs_val > vlock_log_delta_m) &&
+ (vlock_log_delta_en&(1<<4)))
+ pr_info("vlock m delta:%d(0x%x,0x%x)\n",
+ abs_val, ((m_frac_diff_value >> 16) & 0x1ff),
+ (tmp_value & 0x1ff));
+ if ((abs_val <= vlock_pll_m_limit) &&
+ (((m_frac_diff_value >> 16) & 0x1ff) !=
+ (tmp_value & 0x1ff)) &&
+ (abs_cnt > vlock_delta_cnt_limit)) {
+ tmp_value = (tmp_value & 0xfffffe00) |
+ ((m_frac_diff_value >> 16) & 0x1ff);
+ vlock_set_panel_pll_m(tmp_value);
+ vlock_pll_val_last &= 0x0000ffff;
+ vlock_pll_val_last |= (m_frac_diff_value & 0xffff0000);
+ }
+ } else {
+ pre_m = (tmp_value & 0xff);
+ new_m = ((m_frac_diff_value >> 16) & 0xff);
+ org_m = (vlock.val_m & 0xff);
+ if (pre_m != new_m) {
+ if (new_m > pre_m) {
+ tar_m = ((pre_m + 1) <
+ (org_m + 1))?(pre_m + 1):(org_m + 1);
+ } else {
+ /*tar_m < pre_m*/
+ tar_m = ((pre_m - 1) <
+ (org_m - 1))?(org_m - 1):(pre_m - 1);
+ }
+ m_reg_value = (tmp_value & 0xffffff00) + tar_m;
+ if ((pre_m != tar_m) && (m_diff_cnt++ > 5)) {
+ m_diff_cnt = 0;
+ if (vlock_debug & VLOCK_DEBUG_INFO)
+ pr_info("vlock m chg: pre=0x%x, report=0x%x\n",
+ pre_m, new_m);
+ vlock_set_panel_pll_m(m_reg_value);
+ mchange = 1;
+ }
+ }
+ }
+
/*frac*/
tmp_value = vlock_get_panel_pll_frac();
if (vlock.dtdata->vlk_hwver < vlock_hw_ver2) {
frac_reg_value = tmp_value;
/*16:0*/
tmp_value = vlock_get_panel_pll_frac();
- if ((tmp_value & 0x1ffff) != (frac_reg_value & 0x1ffff)) {
+ if (((tmp_value & 0x1ffff) != (frac_reg_value & 0x1ffff))
+ && (f_diff_cnt++ > 3)) {
+ f_diff_cnt = 0;
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("vlock f chg = 0x%x\n",
(frac_reg_value & 0x1ffff));
}
}
- /*m*/
- tmp_value = vlock_get_panel_pll_m();
- if (vlock.dtdata->vlk_hwver < vlock_hw_ver2) {
- abs_val = abs(((m_frac_diff_value >> 16) & 0xff) -
- (pre_hiu_reg_m & 0xff));
- if ((abs_val > vlock_log_delta_m) &&
- (vlock_log_delta_en&(1<<4)))
- pr_info("vlock m delta:%d(0x%x,0x%x)\n",
- abs_val, ((m_frac_diff_value >> 16) & 0x1ff),
- (tmp_value & 0x1ff));
- if ((abs_val <= vlock_pll_m_limit) &&
- (((m_frac_diff_value >> 16) & 0x1ff) !=
- (tmp_value & 0x1ff)) &&
- (abs_cnt > vlock_delta_cnt_limit)) {
- tmp_value = (tmp_value & 0xfffffe00) |
- ((m_frac_diff_value >> 16) & 0x1ff);
- vlock_set_panel_pll_m(tmp_value);
- vlock_pll_val_last &= 0x0000ffff;
- vlock_pll_val_last |= (m_frac_diff_value & 0xffff0000);
- }
- } else {
- pre_m = (tmp_value & 0xff);
- new_m = ((m_frac_diff_value >> 16) & 0xff);
- org_m = (vlock.val_m & 0xff);
- if ((pre_m != new_m) ||
- (frac_reg_value != vlock_get_panel_pll_frac())) {
-
- if (new_m > pre_m) {
- tar_m = ((pre_m + 1) <
- (org_m + 1))?(pre_m + 1):(org_m + 1);
- } else {
- /*tar_m < pre_m*/
- tar_m = ((pre_m - 1) <
- (org_m - 1))?(org_m - 1):(pre_m - 1);
- }
- m_reg_value = (tmp_value & 0xffffff00) + tar_m;
- if (pre_m != tar_m) {
- if (vlock_debug & VLOCK_DEBUG_INFO)
- pr_info("vlock m chg: pre=0x%x, report=0x%x\n",
- pre_m, new_m);
- vlock_set_panel_pll_m(m_reg_value);
- }
- }
- }
-
/*check stable by diff m*/
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
if (((m_frac_diff_value >> 16) & 0xff) != (tmp_value & 0xff))
if (IS_AUTO_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x7, 0, 3);
+ #if 0
else if (IS_MANUAL_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x6, 0, 3);
+ #endif
}
if (vlock_debug & VLOCK_DEBUG_INFO)
if (IS_AUTO_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x7, 0, 3);
+ #if 0
else if (IS_MANUAL_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x6, 0, 3);
+ #endif
}
ret = 1;
case VLOCK_STATE_NULL:
if (vlock.vf_sts) {
/*have frame in*/
- if (vlock.frame_cnt_in++ >= 100) {
+ if (vlock.frame_cnt_in++ >= VLOCK_START_CNT) {
/*vframe input valid*/
if (vlock.md_support) {
if (vlock_fsm_to_en_func(&vlock, vf)) {
case VLOCK_STATE_ENABLE_STEP2_DONE:
if (vlock.vf_sts) {
+ vlock.frame_cnt_in++;
if (!vlock.md_support) {
/*function not support*/
vlock_clear_frame_counter();