intel: Simplify few version checks involving G4X

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index d73718d..2c0b6ef 100644 (file)
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -547,7 +547,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
    s.MOCS = info->mocs;
 #endif
 
-#if GEN_GEN > 4 || GEN_VERSIONx10 == 45
+#if GEN_VERSIONx10 >= 45
    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
       /* There are fairly strict rules about when the offsets can be used.
        * These are mostly taken from the Sky Lake PRM documentation for

diff --git a/src/mesa/drivers/dri/i965/genX_pipe_control.c b/src/mesa/drivers/dri/i965/genX_pipe_control.c
index d0f244b..33ce841 100644 (file)
--- a/src/mesa/drivers/dri/i965/genX_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/genX_pipe_control.c
@@ -492,7 +492,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
       pc.InstructionCacheInvalidateEnable =
          flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE;
       pc.NotifyEnable = flags & PIPE_CONTROL_NOTIFY_ENABLE;
-   #if GEN_GEN >= 5 || GEN_VERSIONx10 == 45
+   #if GEN_GEN >= 45
       pc.IndirectStatePointersDisable =
          flags & PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE;
    #endif

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index a6c780f..6318af4 100644 (file)
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1679,7 +1679,7 @@ genX(upload_sf)(struct brw_context *brw)
          sf.SmoothPointEnable = false;
 #endif
 
-#if GEN_VERSIONx10 == 45 || GEN_GEN >= 5
+#if GEN_VERSIONx10 >= 45
       sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
 #endif