arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, this patch includes fix for SOR powergate node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index a550e7b..909960a 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -796,7 +796,9 @@
                        pd_sor: sor {
                                clocks = <&tegra_car TEGRA210_CLK_SOR0>,
                                         <&tegra_car TEGRA210_CLK_SOR1>,
-                                        <&tegra_car TEGRA210_CLK_CSI>,
+                                        <&tegra_car TEGRA210_CLK_CILAB>,
+                                        <&tegra_car TEGRA210_CLK_CILCD>,
+                                        <&tegra_car TEGRA210_CLK_CILE>,
                                         <&tegra_car TEGRA210_CLK_DSIA>,
                                         <&tegra_car TEGRA210_CLK_DSIB>,
                                         <&tegra_car TEGRA210_CLK_DPAUX>,
@@ -804,7 +806,6 @@
                                         <&tegra_car TEGRA210_CLK_MIPI_CAL>;
                                resets = <&tegra_car TEGRA210_CLK_SOR0>,
                                         <&tegra_car TEGRA210_CLK_SOR1>,
-                                        <&tegra_car TEGRA210_CLK_CSI>,
                                         <&tegra_car TEGRA210_CLK_DSIA>,
                                         <&tegra_car TEGRA210_CLK_DSIB>,
                                         <&tegra_car TEGRA210_CLK_DPAUX>,