S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)

The source of pwm clock is fixed at evt1.
And some registers for pwm clock are removed.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/s5pc2xx/clock.c b/arch/arm/cpu/armv7/s5pc2xx/clock.c
index 624de62..5ecd475 100644 (file)
--- a/arch/arm/cpu/armv7/s5pc2xx/clock.c
+++ b/arch/arm/cpu/armv7/s5pc2xx/clock.c
@@ -124,29 +124,35 @@ static unsigned long s5pc210_get_pwm_clk(void)
        unsigned int sel;
        unsigned int ratio;
 
-       /*
-        * CLK_SRC_PERIL0
-        * PWM_SEL [27:24]
-        */
-       sel = readl(&clk->src_peril0);
-       sel = (sel >> 24) & 0xf;
-
-       if (sel == 0x6)
+       if (s5p_get_cpu_rev() == 0) {
+               /*
+                * CLK_SRC_PERIL0
+                * PWM_SEL [27:24]
+                */
+               sel = readl(&clk->src_peril0);
+               sel = (sel >> 24) & 0xf;
+
+               if (sel == 0x6)
+                       sclk = get_pll_clk(MPLL);
+               else if (sel == 0x7)
+                       sclk = get_pll_clk(EPLL);
+               else if (sel == 0x8)
+                       sclk = get_pll_clk(VPLL);
+               else
+                       return 0;
+
+               /*
+                * CLK_DIV_PERIL3
+                * PWM_RATIO [3:0]
+                */
+               ratio = readl(&clk->div_peril3);
+               ratio = ratio & 0xf;
+       } else if (s5p_get_cpu_rev() == 1) {
                sclk = get_pll_clk(MPLL);
-       else if (sel == 0x7)
-               sclk = get_pll_clk(EPLL);
-       else if (sel == 0x8)
-               sclk = get_pll_clk(VPLL);
-       else
+               ratio = 8;
+       } else
                return 0;
 
-       /*
-        * CLK_DIV_PERIL3
-        * PWM_RATIO [3:0]
-        */
-       ratio = readl(&clk->div_peril3);
-       ratio = ratio & 0xf;
-
        pclk = sclk / (ratio + 1);
 
        return pclk;