ac/llvm,radeonsi: lower nir_load_ring_tess_offchip_amd in abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23433>

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 6593d06..c0bf744 100644 (file)
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -3084,7 +3084,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
    case nir_intrinsic_load_base_vertex:
    case nir_intrinsic_load_first_vertex:
    case nir_intrinsic_load_tess_rel_patch_id_amd:
-   case nir_intrinsic_load_ring_tess_offchip_amd:
    case nir_intrinsic_load_ring_attr_amd:
    case nir_intrinsic_load_ring_gsvs_amd:
    case nir_intrinsic_load_lds_ngg_scratch_base_amd:

diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
index 425bd94..65832d5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
+++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c
@@ -18,6 +18,7 @@ struct lower_abi_state {
    struct si_shader_args *args;
 
    nir_ssa_def *esgs_ring;
+   nir_ssa_def *tess_offchip_ring;
 };
 
 #define GET_FIELD_NIR(field) \
@@ -157,13 +158,18 @@ fetch_framebuffer(nir_builder *b, struct si_shader_args *args,
                                   .access = ACCESS_CAN_REORDER);
 }
 
-static nir_ssa_def *build_tess_factor_ring_desc(nir_builder *b, struct si_screen *screen,
-                                                struct si_shader_args *args)
+static nir_ssa_def *build_tess_ring_desc(nir_builder *b, struct si_screen *screen,
+                                         struct si_shader_args *args)
 {
-   nir_ssa_def *addr = ac_nir_load_arg(b, &args->ac, args->tcs_out_lds_layout);
-   /* TCS only receives high 13 bits of the address. */
-   addr = nir_iand_imm(b, addr, 0xfff80000);
-   addr = nir_iadd_imm(b, addr, screen->hs.tess_offchip_ring_size);
+   nir_ssa_def *addr;
+   if (b->shader->info.stage == MESA_SHADER_TESS_CTRL) {
+      addr = ac_nir_load_arg(b, &args->ac, args->tcs_out_lds_layout);
+      /* TCS only receives high 13 bits of the address. */
+      addr = nir_iand_imm(b, addr, 0xfff80000);
+   } else {
+      assert(b->shader->info.stage == MESA_SHADER_TESS_EVAL);
+      addr = ac_nir_load_arg(b, &args->ac, args->tes_offchip_addr);
+   }
 
    uint32_t rsrc3 =
       S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
@@ -229,6 +235,9 @@ static void preload_reusable_variables(nir_builder *b, struct lower_abi_state *s
        (key->ge.as_es || sel->stage == MESA_SHADER_GEOMETRY)) {
       s->esgs_ring = build_esgs_ring_desc(b, sel->screen->info.gfx_level, s->args);
    }
+
+   if (sel->stage == MESA_SHADER_TESS_CTRL || sel->stage == MESA_SHADER_TESS_EVAL)
+      s->tess_offchip_ring = build_tess_ring_desc(b, sel->screen, s->args);
 }
 
 static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_state *s)
@@ -496,9 +505,13 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
       replacement = fetch_framebuffer(b, args, sel, key);
       break;
    }
-   case nir_intrinsic_load_ring_tess_factors_amd:
-      replacement = build_tess_factor_ring_desc(b, sel->screen, args);
+   case nir_intrinsic_load_ring_tess_factors_amd: {
+      assert(s->tess_offchip_ring);
+      nir_ssa_def *addr = nir_channel(b, s->tess_offchip_ring, 0);
+      addr = nir_iadd_imm(b, addr, sel->screen->hs.tess_offchip_ring_size);
+      replacement = nir_vector_insert_imm(b, s->tess_offchip_ring, addr, 0);
       break;
+   }
    case nir_intrinsic_load_ring_tess_factors_offset_amd:
       replacement = ac_nir_load_arg(b, &args->ac, args->ac.tcs_factor_offset);
       break;
@@ -607,6 +620,10 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
          replacement = ac_nir_load_arg(b, &args->ac, args->ac.tes_rel_patch_id);
       }
       break;
+   case nir_intrinsic_load_ring_tess_offchip_amd:
+      assert(s->tess_offchip_ring);
+      replacement = s->tess_offchip_ring;
+      break;
    default:
       return false;
    }

diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 28f7e16..e2b4932 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -98,7 +98,6 @@ struct si_shader_context {
 
    /* Preloaded descriptors. */
    LLVMValueRef gsvs_ring[4];
-   LLVMValueRef tess_offchip_ring;
    LLVMValueRef instance_divisor_constbuf;
 
    LLVMValueRef gs_ngg_emit;
@@ -200,7 +199,6 @@ void si_llvm_gs_build_end(struct si_shader_context *ctx);
 
 /* si_shader_llvm_tess.c */
 LLVMValueRef si_get_rel_patch_id(struct si_shader_context *ctx);
-void si_llvm_preload_tess_rings(struct si_shader_context *ctx);
 void si_llvm_ls_build_end(struct si_shader_context *ctx);
 void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_part_key *key,
                               bool separate_epilog);

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c
index 7521063..e5371fb 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c
@@ -671,9 +671,6 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin
    struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 
    switch (intrin->intrinsic) {
-   case nir_intrinsic_load_ring_tess_offchip_amd:
-      return ctx->tess_offchip_ring;
-
    case nir_intrinsic_load_tess_rel_patch_id_amd:
       return si_get_rel_patch_id(ctx);
 
@@ -779,11 +776,6 @@ static bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shade
 
    case MESA_SHADER_TESS_CTRL:
       si_llvm_init_tcs_callbacks(ctx);
-      si_llvm_preload_tess_rings(ctx);
-      break;
-
-   case MESA_SHADER_TESS_EVAL:
-      si_llvm_preload_tess_rings(ctx);
       break;
 
    case MESA_SHADER_GEOMETRY:

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
index 897df46..2a26041 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
@@ -212,12 +212,6 @@ static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx, enum
    return ac_build_gather_values(&ctx->ac, desc, 4);
 }
 
-void si_llvm_preload_tess_rings(struct si_shader_context *ctx)
-{
-   ctx->tess_offchip_ring = get_tess_ring_descriptor(
-      ctx, ctx->stage == MESA_SHADER_TESS_CTRL ? TESS_OFFCHIP_RING_TCS : TESS_OFFCHIP_RING_TES);
-}
-
 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi, LLVMTypeRef type,
                                              LLVMValueRef vertex_index, LLVMValueRef param_index,
                                              unsigned driver_location, unsigned component,