reg = <0xffe09000 0x80
0xffd01008 0x100
0xff636000 0x2000
- 0xff63a000 0x2000
- 0xff8000e8 0x10
- 0xff63c100 0x4>;
+ 0xff63a000 0x2000>;
pll-setting-1 = <0x09400414>;
pll-setting-2 = <0x927E0000>;
pll-setting-3 = <0xac5f69e5>;
pll-setting-8 = <0xe000c>;
version = <2>;
pwr-ctl = <1>;
+ u2-ctrl-sleep-shift = <17>;
+ u2-hhi-mem-pd-shift = <30>;
+ u2-hhi-mem-pd-mask = <0x3>;
+ u2-ctrl-iso-shift = <17>;
};
usb3_phy_v2: usb3phy@ffe09080 {
compatible = "amlogic, amlogic-new-usb3-v2";
status = "disable";
reg = <0xffe09080 0x20
- 0xff8000e8 0x10
- 0xff63c100 0x4
0xffd01008 0x100>;
phy-reg = <0xff646000>;
phy-reg-size = <0x2000>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "pcie_refpll";
pwr-ctl = <1>;
+ u3-ctrl-sleep-shift = <18>;
+ u3-hhi-mem-pd-shift = <26>;
+ u3-hhi-mem-pd-mask = <0xf>;
+ u3-ctrl-iso-shift = <18>;
};
dwc2_a: dwc2_a@ff400000 {
0xff648000 0x2000
0xfc400000 0x200000
0xff646000 0x2000
- 0xffd01080 0x10
- 0xff8000e8 0x8
- 0xff63c100 0x4>;
+ 0xffd01080 0x10>;
reg-names = "elbi", "cfg", "config", "phy",
- "reset", "pwr", "hii";
+ "reset";
interrupts = <0 221 0>;
#interrupt-cells = <1>;
bus-range = <0x0 0xff>;
pcie-phy-rst-bit = <14>;
pcie-ctrl-a-rst-bit = <12>;
pwr-ctl = <1>;
+ pcie-ctrl-sleep-shift = <18>;
+ pcie-hhi-mem-pd-shift = <26>;
+ pcie-hhi-mem-pd-mask = <0xf>;
+ pcie-ctrl-iso-shift = <18>;
status = "disabled";
};
reg = <0x0 0xffe09000 0x0 0x80
0x0 0xffd01008 0x0 0x100
0x0 0xff636000 0x0 0x2000
- 0x0 0xff63a000 0x0 0x2000
- 0x0 0xff8000e8 0x0 0x10
- 0x0 0xff63c100 0x0 0x4>;
+ 0x0 0xff63a000 0x0 0x2000>;
pll-setting-1 = <0x09400414>;
pll-setting-2 = <0x927E0000>;
pll-setting-3 = <0xac5f69e5>;
pll-setting-8 = <0xe000c>;
version = <2>;
pwr-ctl = <1>;
+ u2-ctrl-sleep-shift = <17>;
+ u2-hhi-mem-pd-shift = <30>;
+ u2-hhi-mem-pd-mask = <0x3>;
+ u2-ctrl-iso-shift = <17>;
};
usb3_phy_v2: usb3phy@ffe09080 {
compatible = "amlogic, amlogic-new-usb3-v2";
status = "disable";
reg = <0x0 0xffe09080 0x0 0x20
- 0x0 0xff8000e8 0x0 0x10
- 0x0 0xff63c100 0x0 0x4
0x0 0xffd01008 0x0 0x100>;
phy-reg = <0xff646000>;
phy-reg-size = <0x2000>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "pcie_refpll";
pwr-ctl = <1>;
+ u3-ctrl-sleep-shift = <18>;
+ u3-hhi-mem-pd-shift = <26>;
+ u3-hhi-mem-pd-mask = <0xf>;
+ u3-ctrl-iso-shift = <18>;
};
dwc2_a: dwc2_a@ff400000 {
0x0 0xff648000 0x0 0x2000
0x0 0xfc400000 0x0 0x200000
0x0 0xff646000 0x0 0x2000
- 0x0 0xffd01080 0x0 0x10
- 0x0 0xff8000e8 0x0 0x8
- 0x0 0xff63c100 0x0 0x4>;
- reg-names = "elbi", "cfg", "config", "phy",
- "reset", "pwr", "hii";
+ 0x0 0xffd01080 0x0 0x10>;
+ reg-names = "elbi", "cfg", "config", "phy", "reset";
interrupts = <0 221 0>;
#interrupt-cells = <1>;
bus-range = <0x0 0xff>;
pcie-phy-rst-bit = <14>;
pcie-ctrl-a-rst-bit = <12>;
pwr-ctl = <1>;
+ pcie-ctrl-sleep-shift = <18>;
+ pcie-hhi-mem-pd-shift = <26>;
+ pcie-hhi-mem-pd-mask = <0xf>;
+ pcie-ctrl-iso-shift = <18>;
status = "disabled";
};
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/module.h>
+#include <linux/amlogic/power_ctrl.h>
#include "../drivers/pci/host/pcie-designware.h"
#include "pcie-amlogic.h"
{
u32 val;
- writel(readl(phy->power_base) & (~(0x1<<18)), phy->power_base);
+ power_ctrl_sleep(1, phy->pcie_ctrl_sleep_shift);
- writel(readl(phy->hhi_mem_pd_base) & (~(0xf<<26)),
- phy->hhi_mem_pd_base);
+ power_ctrl_mempd0(1, phy->pcie_hhi_mem_pd_mask,
+ phy->pcie_hhi_mem_pd_shift);
udelay(100);
val = readl((void __iomem *)(unsigned long)phy->reset_base);
(void __iomem *)(unsigned long)phy->reset_base);
udelay(100);
- writel(readl(phy->power_base+0x4) & (~(0x1<<18)),
- phy->power_base + 0x4);
+ power_ctrl_iso(1, phy->pcie_ctrl_iso_shift);
val = readl((void __iomem *)(unsigned long)phy->reset_base);
writel((val | (0x1<<12)),
struct resource *phy_base;
struct resource *cfg_base;
struct resource *reset_base;
- struct resource *power_base = NULL;
- struct resource *hhi_mem_pd_base = NULL;
int ret;
int pcie_num = 0;
int num_lanes = 0;
int pcie_phy_rst_bit = 0;
int pcie_ctrl_a_rst_bit = 0;
u32 pwr_ctl = 0;
+ const void *prop;
dev_info(&pdev->dev, "amlogic_pcie_probe!\n");
amlogic_pcie->pwr_ctl = pwr_ctl;
if (pwr_ctl) {
- power_base = platform_get_resource_byname(
- pdev, IORESOURCE_MEM, "pwr");
- if (power_base) {
- amlogic_pcie->phy->power_base =
- ioremap(power_base->start,
- resource_size(power_base));
- if (IS_ERR(amlogic_pcie->phy->power_base))
- return PTR_ERR(amlogic_pcie->phy->power_base);
- }
-
- hhi_mem_pd_base = platform_get_resource_byname(
- pdev, IORESOURCE_MEM, "hii");
- if (hhi_mem_pd_base) {
- amlogic_pcie->phy->hhi_mem_pd_base =
- ioremap(hhi_mem_pd_base->start,
- resource_size(hhi_mem_pd_base));
- if (IS_ERR(amlogic_pcie->phy->hhi_mem_pd_base))
- return PTR_ERR(amlogic_pcie->
- phy->hhi_mem_pd_base);
- }
+ prop = of_get_property(dev->of_node,
+ "pcie-ctrl-sleep-shift", NULL);
+ if (prop)
+ amlogic_pcie->phy->pcie_ctrl_sleep_shift =
+ of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "pcie-hhi-mem-pd-shift", NULL);
+ if (prop)
+ amlogic_pcie->phy->pcie_hhi_mem_pd_shift =
+ of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "pcie-hhi-mem-pd-mask", NULL);
+ if (prop)
+ amlogic_pcie->phy->pcie_hhi_mem_pd_mask =
+ of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "pcie-ctrl-iso-shift", NULL);
+ if (prop)
+ amlogic_pcie->phy->pcie_ctrl_iso_shift =
+ of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
}
if (!amlogic_pcie->phy->reset_base) {
u32 reset_state;
void __iomem *phy_base; /* DT 1st resource */
void __iomem *reset_base;/* DT 3nd resource */
- void __iomem *power_base;
- void __iomem *hhi_mem_pd_base;
+ u32 pcie_ctrl_sleep_shift;
+ u32 pcie_hhi_mem_pd_mask;
+ u32 pcie_ctrl_iso_shift;
+ u32 pcie_hhi_mem_pd_shift;
};
#include <linux/usb/phy.h>
#include <linux/amlogic/usb-v2.h>
#include <linux/amlogic/cpu_version.h>
+#include <linux/amlogic/power_ctrl.h>
#include "phy-aml-new-usb-v2.h"
struct amlogic_usb_v2 *g_phy2_v2;
void power_switch_to_usb(struct amlogic_usb_v2 *phy)
{
/* Powerup usb_comb */
- writel(readl(phy->power_base) & (~(0x1<<17)), phy->power_base);
- writel(readl(phy->hhi_mem_pd_base) & (~(0x3<<30)),
- phy->hhi_mem_pd_base);
+ power_ctrl_sleep(1, phy->u2_ctrl_sleep_shift);
+ power_ctrl_mempd0(1, phy->u2_hhi_mem_pd_mask, phy->u2_hhi_mem_pd_shift);
udelay(100);
writel((readl(phy->reset_regs + (0x21 * 4 - 0x8)) & ~(0x1 << 2)),
phy->reset_regs + (0x21 * 4 - 0x8));
udelay(100);
- writel(readl(phy->power_base+0x4) & (~(0x1<<17)),
- phy->power_base + 0x4);
+ power_ctrl_iso(1, phy->u2_ctrl_iso_shift);
writel((readl(phy->reset_regs + (0x21 * 4 - 0x8)) | (0x1 << 2)),
phy->reset_regs + (0x21 * 4 - 0x8));
struct resource *phy_mem;
struct resource *reset_mem;
struct resource *phy_cfg_mem[4];
- struct resource *power_mem = NULL;
- struct resource *hhi_mem_pd_mem = NULL;
void __iomem *phy_base;
void __iomem *reset_base = NULL;
void __iomem *phy_cfg_base[4];
- void __iomem *power_base = NULL;
- void __iomem *hhi_mem_pd_base = NULL;
int portnum = 0;
int phy_version = 0;
const void *prop;
int retval;
u32 pll_setting[8];
u32 pwr_ctl = 0;
+ u32 u2_ctrl_sleep_shift = 0;
+ u32 u2_hhi_mem_pd_shift = 0;
+ u32 u2_hhi_mem_pd_mask = 0;
+ u32 u2_ctrl_iso_shift = 0;
prop = of_get_property(dev->of_node, "portnum", NULL);
if (prop)
pwr_ctl = 0;
if (pwr_ctl) {
- power_mem = platform_get_resource
- (pdev, IORESOURCE_MEM, 2 + portnum);
- if (power_mem) {
- power_base = ioremap(power_mem->start,
- resource_size(power_mem));
- if (IS_ERR(power_base))
- return PTR_ERR(power_base);
- }
-
- hhi_mem_pd_mem = platform_get_resource
- (pdev, IORESOURCE_MEM, 3 + portnum);
- if (hhi_mem_pd_mem) {
- hhi_mem_pd_base = ioremap(hhi_mem_pd_mem->start,
- resource_size(hhi_mem_pd_mem));
- if (IS_ERR(hhi_mem_pd_base))
- return PTR_ERR(hhi_mem_pd_base);
- }
+ prop = of_get_property(dev->of_node,
+ "u2-ctrl-sleep-shift", NULL);
+ if (prop)
+ u2_ctrl_sleep_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u2-hhi-mem-pd-shift", NULL);
+ if (prop)
+ u2_hhi_mem_pd_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u2-hhi-mem-pd-mask", NULL);
+ if (prop)
+ u2_hhi_mem_pd_mask = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u2-ctrl-iso-shift", NULL);
+ if (prop)
+ u2_ctrl_iso_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
}
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
}
if (pwr_ctl) {
- phy->power_base = power_base;
- phy->hhi_mem_pd_base = hhi_mem_pd_base;
+ phy->u2_ctrl_sleep_shift = u2_ctrl_sleep_shift;
+ phy->u2_hhi_mem_pd_shift = u2_hhi_mem_pd_shift;
+ phy->u2_hhi_mem_pd_mask = u2_hhi_mem_pd_mask;
+ phy->u2_ctrl_iso_shift = u2_ctrl_iso_shift;
power_switch_to_usb(phy);
}
#include <linux/workqueue.h>
#include <linux/notifier.h>
#include <linux/amlogic/usbtype.h>
+#include <linux/amlogic/power_ctrl.h>
#include "phy-aml-new-usb-v2.h"
#define HOST_MODE 0
{
u32 val;
- writel(readl(phy->power_base) & (~(0x1<<18)), phy->power_base);
-
- writel(readl(phy->hhi_mem_pd_base) & (~(0xf<<26)),
- phy->hhi_mem_pd_base);
+ power_ctrl_sleep(1, phy->u3_ctrl_sleep_shift);
+ power_ctrl_mempd0(1, phy->u3_hhi_mem_pd_mask, phy->u3_hhi_mem_pd_shift);
udelay(100);
val = readl((void __iomem *)
((unsigned long)phy->reset_regs + (0x20 * 4 - 0x8)));
udelay(100);
- writel(readl(phy->power_base+0x4) & (~(0x1<<18)),
- phy->power_base + 0x4);
+ power_ctrl_iso(1, phy->u3_ctrl_iso_shift);
+
val = readl((void __iomem *)
((unsigned long)phy->reset_regs + (0x20 * 4 - 0x8)));
writel((val | (0x1<<12)), (void __iomem *)
struct amlogic_usb_v2 *phy;
struct device *dev = &pdev->dev;
struct resource *phy_mem;
- struct resource *power_mem = NULL;
- struct resource *hhi_mem_pd_mem = NULL;
struct resource *reset_mem;
void __iomem *phy_base;
void __iomem *phy3_base;
- void __iomem *power_base = NULL;
- void __iomem *hhi_mem_pd_base = NULL;
void __iomem *reset_base = NULL;
unsigned int phy3_mem;
unsigned int phy3_mem_size = 0;
int ret;
struct device_node *tsi_pci;
u32 pwr_ctl = 0;
+ u32 u3_ctrl_sleep_shift = 0;
+ u32 u3_hhi_mem_pd_shift = 0;
+ u32 u3_hhi_mem_pd_mask = 0;
+ u32 u3_ctrl_iso_shift = 0;
gpio_name = of_get_property(dev->of_node, "gpio-vbus-power", NULL);
if (gpio_name) {
pwr_ctl = 0;
if (pwr_ctl) {
- power_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (power_mem) {
- power_base = ioremap(power_mem->start,
- resource_size(power_mem));
- if (IS_ERR(power_base))
- return PTR_ERR(power_base);
- }
-
- hhi_mem_pd_mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- if (hhi_mem_pd_mem) {
- hhi_mem_pd_base = ioremap(hhi_mem_pd_mem->start,
- resource_size(hhi_mem_pd_mem));
- if (IS_ERR(hhi_mem_pd_base))
- return PTR_ERR(hhi_mem_pd_base);
- }
-
- reset_mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+ reset_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (reset_mem) {
reset_base = ioremap(reset_mem->start,
resource_size(reset_mem));
if (IS_ERR(reset_base))
return PTR_ERR(reset_base);
}
+
+ prop = of_get_property(dev->of_node,
+ "u3-ctrl-sleep-shift", NULL);
+ if (prop)
+ u3_ctrl_sleep_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u3-hhi-mem-pd-shift", NULL);
+ if (prop)
+ u3_hhi_mem_pd_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u3-hhi-mem-pd-mask", NULL);
+ if (prop)
+ u3_hhi_mem_pd_mask = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
+
+ prop = of_get_property(dev->of_node,
+ "u3-ctrl-iso-shift", NULL);
+ if (prop)
+ u3_ctrl_iso_shift = of_read_ulong(prop, 1);
+ else
+ pwr_ctl = 0;
}
retval = of_property_read_u32
/* set the phy from pcie to usb3 */
if (phy->portnum > 0) {
if (phy->pwr_ctl) {
- phy->power_base = power_base;
- phy->hhi_mem_pd_base = hhi_mem_pd_base;
+ phy->u3_ctrl_sleep_shift = u3_ctrl_sleep_shift;
+ phy->u3_hhi_mem_pd_shift = u3_hhi_mem_pd_shift;
+ phy->u3_hhi_mem_pd_mask = u3_hhi_mem_pd_mask;
+ phy->u3_ctrl_iso_shift = u3_ctrl_iso_shift;
phy->reset_regs = reset_base;
power_switch_to_pcie(phy);
}
void __iomem *phy3_cfg_r4;
void __iomem *phy3_cfg_r5;
void __iomem *usb2_phy_cfg;
- void __iomem *power_base;
- void __iomem *hhi_mem_pd_base;
u32 pll_setting[8];
int phy_cfg_state[4];
/* Set VBus Power though GPIO */
int suspend_flag;
int phy_version;
int pwr_ctl;
+ u32 u2_ctrl_sleep_shift;
+ u32 u2_hhi_mem_pd_mask;
+ u32 u2_ctrl_iso_shift;
+ u32 u2_hhi_mem_pd_shift;
+ u32 u3_ctrl_sleep_shift;
+ u32 u3_hhi_mem_pd_mask;
+ u32 u3_ctrl_iso_shift;
+ u32 u3_hhi_mem_pd_shift;
struct clk *clk;
};
projects / platform / kernel / linux-amlogic.git / commitdiff