x86: Add a clock driver for Intel devices

So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.

This driver can be expanded later as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 16d4237..1992d4a 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -73,6 +73,16 @@ config CLK_COMPOSITE_CCF
          Enable this option if you want to (re-)use the Linux kernel's Common
          Clock Framework [CCF] composite code in U-Boot's clock driver.
 
+config CLK_INTEL
+       bool "Enable clock driver for Intel x86"
+       depends on CLK && X86
+       help
+         This provides very basic support for clocks on Intel SoCs. The driver
+         is barely used at present but could be expanded as needs arise.
+         Much clock configuration in U-Boot is either set up by the FSP, or
+         set up by U-Boot itself but only statically. Thus the driver does not
+         support changing clock rates, only querying them.
+
 config CLK_STM32F
        bool "Enable clock driver support for STM32F family"
        depends on CLK && (STM32F7 || STM32F4)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 06131ed..e017833 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_MVEBU) += mvebu/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
+obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/

diff --git a/drivers/clk/intel/Makefile b/drivers/clk/intel/Makefile
new file mode 100644 (file)
index 0000000..45e93d7
--- /dev/null
+++ b/drivers/clk/intel/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2010 Google LLC
+#
+
+obj-y += clk_intel.o

diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c
new file mode 100644 (file)
index 0000000..d2e1549
--- /dev/null
+++ b/drivers/clk/intel/clk_intel.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk-uclass.h>
+#include <dt-bindings/clock/intel-clock.h>
+
+static ulong intel_clk_get_rate(struct clk *clk)
+{
+       ulong rate;
+
+       switch (clk->id) {
+       case CLK_I2C:
+               /* Hard-coded to 133MHz on current platforms */
+               return 133333333;
+       default:
+               return -ENODEV;
+       }
+
+       return rate;
+}
+
+static struct clk_ops intel_clk_ops = {
+       .get_rate       = intel_clk_get_rate,
+};
+
+static const struct udevice_id intel_clk_ids[] = {
+       { .compatible = "intel,apl-clk" },
+       { }
+};
+
+U_BOOT_DRIVER(clk_intel) = {
+       .name           = "clk_intel",
+       .id             = UCLASS_CLK,
+       .of_match       = intel_clk_ids,
+       .ops            = &intel_clk_ops,
+};

diff --git a/include/dt-bindings/clock/intel-clock.h b/include/dt-bindings/clock/intel-clock.h
new file mode 100644 (file)
index 0000000..e1edd3c
--- /dev/null
+++ b/include/dt-bindings/clock/intel-clock.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Intel clocks.
+ *
+ * The constants defined in this header are used in the device tree
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _DT_BINDINGS_CLK_INTEL_H
+#define _DT_BINDINGS_CLK_INTEL_H
+
+#define CLK_I2C                1
+
+#endif