phy: ti: phy-j721e-wiz: fix usxgmii configuration

Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in
wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL
was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to
LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However,
since the USXGMII mode can support up to 10.3125 Gbps data rate, the
aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and
LANE_MODE_GEN2 respectively. The signal corresponding to the USXGMII lane
of the SERDES has been measured as 5 Gbps without the change and 10 Gbps
with the change. Hence, fix the configuration accordingly to support
USXGMII up to 10G.

Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241012053937.3596885-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index a6c0c5607ffd7b2bba2b987a42d0d80f8d7db62f..c6e846d385d284a611ba4653b328315d8079b7f3 100644 (file)
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -450,8 +450,8 @@ static int wiz_mode_select(struct wiz *wiz)
                } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
                        ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
                        ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
-                       ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
-                       mode = LANE_MODE_GEN1;
+                       ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2);
+                       mode = LANE_MODE_GEN2;
                } else {
                        continue;
                }