intel/genxml: Add COMPCS0 aux-table registers
authorJordan Justen <jordan.l.justen@intel.com>
Fri, 20 Mar 2020 20:29:55 +0000 (13:29 -0700)
committerMarge Bot <emma+marge@anholt.net>
Fri, 7 Jul 2023 18:05:47 +0000 (18:05 +0000)
Bspec 43904 defines COMPCS0_CCS_AUX_INV to 042C8h and Bspec 43882
defines COMPCS0_AUX_TABLE_BASE_ADDR to 042C4h.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958>

src/intel/genxml/gen12.xml
src/intel/genxml/gen125.xml

index a7e6c11..06183bf 100644 (file)
     <field name="Enable Hardware Filtering in WM" start="5" end="5" type="bool" />
     <field name="Enable Hardware Filtering in WM Mask" start="21" end="21" type="bool" />
   </register>
+  <register name="COMPCS0_AUX_TABLE_BASE_ADDR" length="2" num="0x42C0">
+    <field name="Address" start="0" end="63" type="uint" />
+  </register>
+  <register name="COMPCS0_CCS_AUX_INV" length="1" num="0x42C8">
+    <field name="Aux Inv" start="0" end="0" type="bool" />
+  </register>
   <register name="CS_CHICKEN1" length="1" num="0x2580">
     <field name="Replay Mode" start="0" end="0" type="uint">
       <value name="Mid-cmdbuffer Preemption" value="0" />
index 7ac8b3a..7268f20 100644 (file)
     <field name="Enable Hardware Filtering in WM" start="5" end="5" type="bool" />
     <field name="Enable Hardware Filtering in WM Mask" start="21" end="21" type="bool" />
   </register>
+  <register name="COMPCS0_AUX_TABLE_BASE_ADDR" length="2" num="0x42C0">
+    <field name="Address" start="0" end="63" type="uint" />
+  </register>
+  <register name="COMPCS0_CCS_AUX_INV" length="1" num="0x42C8">
+    <field name="Aux Inv" start="0" end="0" type="bool" />
+  </register>
   <register name="CS_CHICKEN1" length="1" num="0x2580">
     <field name="Replay Mode" start="0" end="0" type="uint">
       <value name="Mid-cmdbuffer Preemption" value="0" />