def InstFormatCIW : InstFormat<11>;
def InstFormatCL : InstFormat<12>;
def InstFormatCS : InstFormat<13>;
-def InstFormatCB : InstFormat<14>;
-def InstFormatCJ : InstFormat<15>;
-def InstFormatOther : InstFormat<16>;
+def InstFormatCA : InstFormat<14>;
+def InstFormatCB : InstFormat<15>;
+def InstFormatCJ : InstFormat<16>;
+def InstFormatOther : InstFormat<17>;
-// The following opcode names and match those given in Table 19.1 in the
+// The following opcode names match those given in Table 19.1 in the
// RISC-V User-level ISA specification ("RISC-V base opcode map").
class RISCVOpcode<bits<7> val> {
bits<7> Value = val;
let Inst{1-0} = opcode;
}
+class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> {
+ bits<3> rs2;
+ bits<3> rs1;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{6-5} = funct2;
+ let Inst{4-2} = rs2;
+ let Inst{1-0} = opcode;
+}
+
class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
string opcodestr, string argstr>
: RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> {
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class CS_ALU<bits<2> funct2, string OpcodeStr, RegisterClass cls,
- bit RV64only>
- : RVInst16CS<0b100, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
+class CS_ALU<bits<6> funct6, bits<2> funct2, string OpcodeStr,
+ RegisterClass cls>
+ : RVInst16CA<funct6, funct2, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
OpcodeStr, "$rd, $rs2"> {
bits<3> rd;
let Constraints = "$rd = $rd_wb";
- let Inst{12} = RV64only;
- let Inst{11-10} = 0b11;
let Inst{9-7} = rd;
- let Inst{6-5} = funct2;
}
//===----------------------------------------------------------------------===//
let Inst{6-2} = imm{4-0};
}
-def C_SUB : CS_ALU<0b00, "c.sub", GPRC, 0>;
-def C_XOR : CS_ALU<0b01, "c.xor", GPRC, 0>;
-def C_OR : CS_ALU<0b10, "c.or" , GPRC, 0>;
-def C_AND : CS_ALU<0b11, "c.and", GPRC, 0>;
+def C_SUB : CS_ALU<0b100011, 0b00, "c.sub", GPRC>;
+def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>;
+def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>;
+def C_AND : CS_ALU<0b100011, 0b11, "c.and", GPRC>;
let Predicates = [HasStdExtC, IsRV64] in {
-def C_SUBW : CS_ALU<0b00, "c.subw", GPRC, 1>;
-def C_ADDW : CS_ALU<0b01, "c.addw", GPRC, 1>;
+def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>;
+def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in