MIPS: dts: mscc: describe the PTP ready interrupt

This patch adds a description of the PTP ready interrupt, which can be
triggered when a PTP timestamp is available on an hardware FIFO.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: davem@davemloft.net
Cc: richardcochran@gmail.com
Cc: alexandre.belloni@bootlin.com
Cc: UNGLinuxDriver@microchip.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: allan.nielsen@microchip.com

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 1e55a77..797d336 100644 (file)
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -139,8 +139,8 @@
                                    "port2", "port3", "port4", "port5", "port6",
                                    "port7", "port8", "port9", "port10", "qsys",
                                    "ana", "s2";
-                       interrupts = <21 22>;
-                       interrupt-names = "xtr", "inj";
+                       interrupts = <18 21 22>;
+                       interrupt-names = "ptp_rdy", "xtr", "inj";
 
                        ethernet-ports {
                                #address-cells = <1>;