arm/exynos: add asynchronous bridge clock bindings

The patch adds bindings for clocks required by async-bridges
present in the particular power domain.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 1e097037349c326a22e3f07abb3e3aca9d78d0ce..5da38c5ed476ee2248432314c0bf886305f6cc13 100644 (file)
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,9 @@ Optional Properties:
        - pclkN, clkN: Pairs of parent of input clock and input clock to the
                devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
                are supported currently.
+       - asbN: Clocks required by asynchronous bridges (ASB) present in
+               the power domain. These clock should be enabled during power
+               domain on/off operations.
 - power-domains: phandle pointing to the parent power domain, for more details
                 see Documentation/devicetree/bindings/power/power_domain.txt