dts: spicc: add node for g12a_s905d2 skt.
authorSunny Luo <sunny.luo@amlogic.com>
Mon, 19 Mar 2018 03:37:07 +0000 (11:37 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Wed, 21 Mar 2018 11:55:16 +0000 (03:55 -0800)
PD#162464: dts: spicc: add node for g12a_s905d2 skt

kernel4.9 still use the amlogic driver. DTS compatible name should be
"spicc" but not "meson-g12a-spicc" to avoid probing the upstream driver.

Change-Id: I0465f71f1504929a459ae1d912cc4bb1f397ccde
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
arch/arm64/boot/dts/amlogic/g12a_s905d2_skt.dts
arch/arm64/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts
arch/arm64/boot/dts/amlogic/mesong12a.dtsi

index d18b67a..891eed9 100644 (file)
 
 /* Audio Related End */
 
+&spicc0 {
+       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spicc0_pins_x>;
+       cs-gpios = <&gpio GPIOX_10 0>;
+       num_chipselect = <1>;
+};
+
+&spicc1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spicc1_pins>;
+       cs-gpios = <&gpio GPIOH_6 0>;
+       num_chipselect = <1>;
+};
+
 &pwm_ef {
        status = "okay";
 };
index 7659f4b..82fd333 100644 (file)
 
 /* Audio Related End */
 
+&spicc0 {
+       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spicc0_pins_x>;
+       cs-gpios = <&gpio GPIOX_10 0>;
+       num_chipselect = <1>;
+};
+
+&spicc1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spicc1_pins>;
+       cs-gpios = <&gpio GPIOH_6 0>;
+       num_chipselect = <1>;
+};
+
 &pwm_ef {
        status = "okay";
 };
index 4983994..b8b366d 100644 (file)
                                clock-names = "clk_i2c";
                        };
 
+                       spicc0: spi@13000 {
+                               compatible = "amlogic, spicc";
+                               reg = <0x0 0x13000 0x0 0x40>;
+                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                               clock-names = "spicc_clk";
+                               clocks = <&clkc CLKID_SPICC0_COMP>;
+                               clk_rate = <666666666>;
+                               device_id = <0>;
+                               enhance = <1>;
+                               ssctl = <0>;
+                               dma_tx_threshold = <3>;
+                               dma_num_per_read_burst = <13>;
+                               dma_auto_param = <1>;
+                               delay_control = <0x15>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spicc1: spi@15000 {
+                               compatible = "amlogic, spicc";
+                               reg = <0x0 0x15000 0x0 0x40>;
+                               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                               clock-names = "spicc_clk";
+                               clocks = <&clkc CLKID_SPICC1_COMP>;
+                               clk_rate = <666666666>;
+                               device_id = <1>;
+                               enhance = <1>;
+                               ssctl = <0>;
+                               dma_tx_threshold = <3>;
+                               dma_num_per_read_burst = <13>;
+                               dma_auto_param = <1>;
+                               delay_control = <0x15>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                }; /* end of cbus */
 
                aobus: aobus@ff800000 {
                };
        };
 
+       spicc0_pins_x: spicc0_pins_x {
+               mux {
+                       groups = "spi0_mosi_x",
+                                "spi0_miso_x",
+                                //"spi0_ss0_x",
+                                "spi0_clk_x";
+                       function = "spi0";
+               };
+       };
+
+       spicc1_pins: spicc1_pins {
+               mux {
+                       groups = "spi1_mosi",
+                                "spi1_miso",
+                                //"spi1_ss0",
+                                "spi1_clk";
+                       function = "spi1";
+               };
+       };
+
        a_uart_pins:a_uart {
                mux {
                        groups = "uart_tx_a",