[NDS32] Restrict mov pattern that has at least one register operand.
authorKito Cheng <kito.cheng@gmail.com>
Wed, 4 Apr 2018 12:38:04 +0000 (12:38 +0000)
committerChung-Ju Wu <jasonwucj@gcc.gnu.org>
Wed, 4 Apr 2018 12:38:04 +0000 (12:38 +0000)
gcc/
* config/nds32/nds32-doubleword.md (move_<mode>): Require
resiter_operand condition.
* config/nds32/nds32.md (*move<mode>): Ditto.

From-SVN: r259077

gcc/ChangeLog
gcc/config/nds32/nds32-doubleword.md
gcc/config/nds32/nds32.md

index 8f97ac2..bd0c1b1 100644 (file)
@@ -1,4 +1,10 @@
 2018-04-04  Kito Cheng  <kito.cheng@gmail.com>
+
+       * config/nds32/nds32-doubleword.md (move_<mode>): Require
+       resiter_operand condition.
+       * config/nds32/nds32.md (*move<mode>): Ditto.
+
+2018-04-04  Kito Cheng  <kito.cheng@gmail.com>
            Monk Chiang  <sh.chiang04@gmail.com>
 
        * config/nds32/nds32.md (movmisalign<mode>): New pattern.
index beefca4..0e4b0dc 100644 (file)
@@ -48,7 +48,8 @@
 (define_insn "move_<mode>"
   [(set (match_operand:DIDF 0 "nonimmediate_operand" "=r, r, r, m")
        (match_operand:DIDF 1 "general_operand"      " r, i, m, r"))]
-  ""
+  "register_operand(operands[0], <MODE>mode)
+   || register_operand(operands[1], <MODE>mode)"
 {
   rtx addr;
   rtx otherops[5];
index 68fe1b3..afbea8b 100644 (file)
 (define_insn "*mov<mode>"
   [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m,   l,   l,   l,   d, r,    d,    r,    r,    r")
        (match_operand:QIHISI 1 "nds32_move_operand"   " r, r,   l,   l,   l,   d, r, U45, U33, U37, U45, m, Ip05, Is05, Is20, Ihig"))]
-  ""
+  "register_operand(operands[0], <MODE>mode)
+   || register_operand(operands[1], <MODE>mode)"
 {
   switch (which_alternative)
     {