[AMDGPU][GFX90A+] Disabled ds_ordered_count and exp

Differential Revision: https://reviews.llvm.org/D124087

diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 4d78e3dae2ec8b46bd06629045f2885451d91043..bc2722e0275945ad42f0908218e09f44c232f06b 100644 (file)
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -626,6 +626,8 @@ def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
 
 def DS_CONSUME       : DS_0A_RET<"ds_consume">;
 def DS_APPEND        : DS_0A_RET<"ds_append">;
+
+let SubtargetPredicate = isNotGFX90APlus in
 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
index b3b55ddd2c97a956d4a9c3c7d76df44d031e033c..3654b8b6232987acdc64feed8ede7223ef08dc61 100644 (file)
--- a/llvm/lib/Target/AMDGPU/EXPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -45,8 +45,10 @@ class EXP_Real<bit done, string pseudo, int subtarget>
 
 // Split EXP instruction into EXP and EXP_DONE so we can set
 // mayLoad for done=1.
+let SubtargetPredicate = isNotGFX90APlus in {
 def EXP : EXP_Pseudo<0>;
 def EXP_DONE : EXP_Pseudo<1>;
+} // let SubtargetPredicate = isNotGFX90APlus
 
 //===----------------------------------------------------------------------===//
 // SI
@@ -69,6 +71,7 @@ def EXP_DONE_si : EXP_Real_si<1, "EXP_DONE">;
 class EXP_Real_vi<bit _done, string pseudo>
   : EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
   let AssemblerPredicate = isGFX8GFX9;
+  let SubtargetPredicate = isNotGFX90APlus;
   let DecoderNamespace = "GFX8";
   let done = _done;
 }

diff --git a/llvm/test/MC/AMDGPU/gfx90a_err.s b/llvm/test/MC/AMDGPU/gfx90a_err.s
index 3388db0c94a81f431d66a766207f15a494f79b1b..69937d9fa9077ba39ec939dc9d3bd527d119e502 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx90a_err.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_err.s
@@ -278,3 +278,9 @@ ds_gws_barrier a3 offset:4 gds
 
 ds_gws_barrier a255 offset:4 gds
 // GFX90A: error: vgpr must be even aligned
+
+ds_ordered_count v5, v1 offset:65535 gds
+// GFX90A: error: instruction not supported on this GPU
+
+exp pos0 v3, v2, v1, v0
+// GFX90A: error: instruction not supported on this GPU

diff --git a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
index 5a92327d32cfd2e803b8fe4855965ddb9662601c..a6c6aa71521312d9b6512b335534c56e8967fb6b 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
@@ -10333,30 +10333,6 @@ ds_append a5 offset:4
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 ds_append a5 offset:65535 gds
 
-// GFX90A: ds_ordered_count a5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a5, v1 offset:65535 gds
-
-// GFX90A: ds_ordered_count a255, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a255, v1 offset:65535 gds
-
-// GFX90A: ds_ordered_count a5, v255 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a5, v255 offset:65535 gds
-
-// GFX90A: ds_ordered_count a5, v1 gds     ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a5, v1 gds
-
-// GFX90A: ds_ordered_count a5, v1 gds     ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a5, v1 gds
-
-// GFX90A: ds_ordered_count a5, v1 offset:4 gds ; encoding: [0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-// NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
-ds_ordered_count a5, v1 offset:4 gds
-
 // GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00]
 // NOT-GFX90A: error: invalid register class: agpr loads and stores not supported on this GPU
 ds_write_b96 v1, a[2:4] offset:65535

diff --git a/llvm/test/MC/AMDGPU/gfx940_err.s b/llvm/test/MC/AMDGPU/gfx940_err.s
index a0b9ec84e65780db583d2cbbb4c95d02d26c4faf..3fc776f5cc314e69f9a66781a7d1b95d1aa64e8b 100644 (file)
--- a/llvm/test/MC/AMDGPU/gfx940_err.s
+++ b/llvm/test/MC/AMDGPU/gfx940_err.s
@@ -78,3 +78,9 @@ s_getreg_b32 s1, hwreg(HW_REG_HW_ID2)
 
 s_getreg_b32 s1, hwreg(HW_REG_POPS_PACKER)
 // GFX940: error: specified hardware register is not supported on this GPU
+
+ds_ordered_count v5, v1 offset:65535 gds
+// GFX940: error: instruction not supported on this GPU
+
+exp pos0 v3, v2, v1, v0
+// GFX940: error: instruction not supported on this GPU

diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
index 0688cd71537de84d128ba2d60dce9952b6c86613..20078d6e4b8ce1ca70bae89b79e0d9c108c47e39 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
@@ -7749,24 +7749,6 @@
 # GFX90A: ds_append a5 offset:65535 gds   ; encoding: [0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05]
 0xff,0xff,0x7d,0xdb,0x00,0x00,0x00,0x05
 
-# GFX90A: ds_ordered_count a5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05]
-0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0x05
-
-# GFX90A: ds_ordered_count a255, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff]
-0xff,0xff,0x7f,0xdb,0x01,0x00,0x00,0xff
-
-# GFX90A: ds_ordered_count a5, v255 offset:65535 gds ; encoding: [0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05]
-0xff,0xff,0x7f,0xdb,0xff,0x00,0x00,0x05
-
-# GFX90A: ds_ordered_count a5, v1 gds     ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
-
-# GFX90A: ds_ordered_count a5, v1 gds     ; encoding: [0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-0x00,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
-
-# GFX90A: ds_ordered_count a5, v1 offset:4 gds ; encoding: [0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05]
-0x04,0x00,0x7f,0xdb,0x01,0x00,0x00,0x05
-
 # GFX90A: ds_write_b96 v1, a[2:4] offset:65535 ; encoding: [0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00]
 0xff,0xff,0xbc,0xdb,0x01,0x02,0x00,0x00