+2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
+
+ * gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for
+ instructions generated instead of number of occurances.
+
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New.
DEF_MULL2 (DEF_MULLH)
DEF_MULL2 (DEF_MULLS)
-/* { dg-final { scan-assembler-times "smull v" 3 } } */
-/* { dg-final { scan-assembler-times "smull2 v" 3 } } */
-/* { dg-final { scan-assembler-times "umull v" 3 } } */
-/* { dg-final { scan-assembler-times "umull2 v" 3 } } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */