}
// 1. Multiply the number of v-slots to the length of registers
- Register FactorRegister = TII->getVLENFactoredAmount(MF, MBB, MBBI, Amount);
+ Register FactorRegister =
+ TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount);
// 2. SP = SP - RVV stack size
BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
.addReg(SPReg)
Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator II,
+ const DebugLoc &DL,
int64_t Amount) const {
assert(Amount > 0 && "There is no need to get VLEN scaled value.");
assert(Amount % 8 == 0 &&
MachineRegisterInfo &MRI = MF.getRegInfo();
const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
- DebugLoc DL = II->getDebugLoc();
int64_t NumOfVReg = Amount / 8;
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator II,
- int64_t Amount) const;
+ const DebugLoc &DL, int64_t Amount) const;
Optional<std::pair<unsigned, unsigned>>
isRVVSpillForZvlsseg(unsigned Opcode) const;
}
// 1. Get vlenb && multiply vlen with the number of vector registers.
ScalableFactorRegister =
- TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
+ TII->getVLENFactoredAmount(MF, MBB, II, DL, ScalableValue);
}
if (!isInt<12>(Offset.getFixed())) {
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -o - %s \
+# RUN: -stop-after=prologepilog | FileCheck %s
+
+--- |
+ define void @foo() !dbg !0 {
+ entry:
+ %va = alloca <vscale x 2 x i32>, align 4, !dbg !1
+ br label %end
+ end:
+ ret void, !dbg !2
+ }
+
+ !0 = distinct !DISubprogram(name: "foo", line: 3, scopeLine: 3)
+ !1 = !DILocation(line: 4, column: 14, scope: !0)
+ !2 = !DILocation(line: 5, column: 3, scope: !0)
+
+...
+---
+name: foo
+tracksRegLiveness: true
+stack:
+ - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 }
+body: |
+ ; CHECK-LABEL: name: foo
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: $x2 = frame-setup ADDI $x2, -16
+ ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
+ ; CHECK: $x10 = PseudoReadVLENB
+ ; CHECK: $x10 = SLLI killed $x10, 1
+ ; CHECK: $x2 = SUB $x2, killed $x10
+ ; CHECK: bb.1:
+ ; CHECK: $x10 = PseudoReadVLENB
+ ; CHECK: $x10 = SLLI killed $x10, 1
+ ; CHECK: $x2 = ADD $x2, killed $x10
+ ; CHECK: $x2 = frame-destroy ADDI $x2, 16
+ ; CHECK: PseudoRET
+ bb.0:
+ bb.1:
+ PseudoRET