Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp.
These will be used for emitting cache control instructions dcbfl and dcbflp
which are actually mnemonics for using dcbf instruction with different
immediate arguments.
dcbfl ra, rb -> dcbf ra, rb, 1
dcbflp, ra, rb -> dcbf ra, rb, 3
Differential Revision: https://reviews.llvm.org/D68411
def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
Intrinsic<[], [llvm_ptr_ty], []>;
+ def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], []>;
+ def int_ppc_dcbflp: Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
+def : Pat<(int_ppc_dcbfl xoaddr:$dst),
+ (DCBFL xoaddr:$dst)>;
+def : Pat<(int_ppc_dcbflp xoaddr:$dst),
+ (DCBFLP xoaddr:$dst)>;
+
def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
}
declare void @llvm.ppc.dcbf(i8*)
+
+; Function Attrs: nounwind
+define void @dcbfl_test(i8* %a) {
+entry:
+ tail call void @llvm.ppc.dcbfl(i8* %a)
+; CHECK-LABEL: @dcbfl_test
+; CHECK: dcbfl 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbfl(i8*)
+
+; Function Attrs: nounwind
+define void @dcbflp_test(i8* %a) {
+entry:
+ %add.a = getelementptr inbounds i8, i8* %a, i64 3
+ tail call void @llvm.ppc.dcbflp(i8* %add.a)
+; CHECK-LABEL: @dcbflp_test
+; CHECK: addi r3, r3, 3
+; CHECK-NEXT: dcbflp 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbflp(i8*)