arm64: dts: renesas: r9a07g044: Add ADC node

Add ADC node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210804202118.25745-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 22fa8de..61b1827 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -169,6 +169,48 @@
                        status = "disabled";
                };
 
+               adc: adc@10059000 {
+                       compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
+                       reg = <0 0x10059000 0 0x400>;
+                       interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
+                                <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
+                       clock-names = "adclk", "pclk";
+                       resets = <&cpg R9A07G044_ADC_PRESETN>,
+                                <&cpg R9A07G044_ADC_ADRST_N>;
+                       reset-names = "presetn", "adrst-n";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0>;
+                       };
+                       channel@1 {
+                               reg = <1>;
+                       };
+                       channel@2 {
+                               reg = <2>;
+                       };
+                       channel@3 {
+                               reg = <3>;
+                       };
+                       channel@4 {
+                               reg = <4>;
+                       };
+                       channel@5 {
+                               reg = <5>;
+                       };
+                       channel@6 {
+                               reg = <6>;
+                       };
+                       channel@7 {
+                               reg = <7>;
+                       };
+               };
+
                cpg: clock-controller@11010000 {
                        compatible = "renesas,r9a07g044-cpg";
                        reg = <0 0x11010000 0 0x10000>;