drm/i915/chv: Add some workaround notes
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 28 Apr 2014 11:31:09 +0000 (14:31 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 20 May 2014 13:20:05 +0000 (15:20 +0200)
We implement the following workarounds:
* WaDisableAsyncFlipPerfMode:chv
* WaProgramMiArbOnOffAroundMiSetContext:chv

v2: Drop WaDisableSemaphoreAndSyncFlipWait note

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/intel_ringbuffer.c

index 50875f5..f220c94 100644 (file)
@@ -568,7 +568,7 @@ mi_set_context(struct intel_ring_buffer *ring,
        if (ret)
                return ret;
 
-       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
+       /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
        if (INTEL_INFO(ring->dev)->gen >= 7)
                intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
        else
index 93b4062..72bf57f 100644 (file)
@@ -610,7 +610,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
         * to use MI_WAIT_FOR_EVENT within the CS. It should already be
         * programmed to '1' on all products.
         *
-        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
+        * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
         */
        if (INTEL_INFO(dev)->gen >= 6)
                I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));