drm/amd/display: add missing interrupt handlers for DCN32/DCN321

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
index 3f9d6531c5633a890e0b5e994f65c4a7708da146..3a213ca2f07717557ba233ac43654283c5c50b65 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -54,6 +54,18 @@ enum dc_irq_source to_dal_irq_source_dcn32(
                return DC_IRQ_SOURCE_VBLANK5;
        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK6;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
+       case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC3_VLINE0;
+       case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC4_VLINE0;
+       case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC5_VLINE0;
+       case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC6_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -78,7 +90,8 @@ enum dc_irq_source to_dal_irq_source_dcn32(
                return DC_IRQ_SOURCE_VUPDATE5;
        case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
                return DC_IRQ_SOURCE_VUPDATE6;
-
+       case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+               return DC_IRQ_SOURCE_DMCUB_OUTBOX;
        case DCN_1_0__SRCID__DC_HPD1_INT:
                /* generic src_id for all HPD and HPDRX interrupts */
                switch (ext_id) {
@@ -168,6 +181,16 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
        .ack = NULL
 };
 
+static const struct irq_source_info_funcs outbox_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -179,6 +202,10 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
        BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
                        reg ## block ## id ## _ ## reg_name
 
+#define SRI_DMUB(reg_name)\
+       BASE(reg ## reg_name ## _BASE_IDX) + \
+                       reg ## reg_name
+
 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
        .enable_reg = SRI(reg1, block, reg_num),\
        .enable_mask = \
@@ -193,6 +220,20 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
        .ack_value = \
                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+       .enable_reg = SRI_DMUB(reg1),\
+       .enable_mask = \
+               reg1 ## __ ## mask1 ## _MASK,\
+       .enable_value = {\
+               reg1 ## __ ## mask1 ## _MASK,\
+               ~reg1 ## __ ## mask1 ## _MASK \
+       },\
+       .ack_reg = SRI_DMUB(reg2),\
+       .ack_mask = \
+               reg2 ## __ ## mask2 ## _MASK,\
+       .ack_value = \
+               reg2 ## __ ## mask2 ## _MASK \
+
 #define hpd_int_entry(reg_num)\
        [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
                IRQ_REG_ENTRY(HPD, reg_num,\
@@ -237,6 +278,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
 }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+#define dmub_outbox_int_entry()\
+       [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+               IRQ_REG_ENTRY_DMUB(\
+                       DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+                       DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+               .funcs = &outbox_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() \
        {\
                .funcs = &dummy_irq_info_funcs\
@@ -339,6 +395,13 @@ irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
        vblank_int_entry(1),
        vblank_int_entry(2),
        vblank_int_entry(3),
+       vline0_int_entry(0),
+       vline0_int_entry(1),
+       vline0_int_entry(2),
+       vline0_int_entry(3),
+       [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+       [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+       dmub_outbox_int_entry(),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn32 = {