riscv: dts: starfive: jh7110: display subsystem

Add the dc controller and hdmi node for the Starfive JH7110 SoC.

[jh80.chung: taken from https://patchew.org/linux/20231204123315.28456-1-keith.zhao@starfivetech.com/]

Change-Id: Ibc45e2ea87759d6b945e33abd2e5d14f42027bb0
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2c02358..b455c20 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -35,6 +35,25 @@
                reg = <0x0 0x40000000 0x1 0x0>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               /* vout applies for space from this CMA
+                * Without this CMA reservation,
+                * vout may not work properly.
+                */
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x20000000>;
+                       alignment = <0x0 0x1000>;
+                       alloc-ranges = <0x0 0x70000000 0x0 0x20000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-restart {
                compatible = "gpio-restart";
                gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
@@ -42,6 +61,68 @@
        };
 };
 
+&dc8200 {
+       status = "okay";
+
+       crtc_out: ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               dc_out0: port@0 {
+                       reg = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dc_out_dpi0: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_enc>;
+                       };
+
+               };
+
+               dc_out1: port@1 {
+                       reg = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dc_out_dpi1: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&dsi_enc>;
+                       };
+
+               };
+       };
+};
+
+&display {
+       status = "okay";
+       ports = <&crtc_out>;
+};
+
+&dsi_encoder {
+       status = "okay";
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               /* input */
+               enc_in: port@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+                       dsi_enc:endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&dc_out_dpi1>;
+                       };
+               };
+               /* output */
+               enc_out: port@1 {
+                       reg = <1>;
+                       /*need add a remote-endpoint to dsi bridge*/
+               };
+       };
+};
+
 &dvp_clk {
        clock-frequency = <74250000>;
 };
@@ -62,6 +143,21 @@
        clock-frequency = <50000000>;
 };
 
+&hdmi {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&hdmi_pins>;
+
+       hdmi_in: port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               hdmi_enc: endpoint@0 {
+                       reg = <0>;
+                       remote-endpoint = <&dc_out_dpi0>;
+               };
+       };
+};
+
 &hdmitx0_pixelclk {
        clock-frequency = <297000000>;
 };
@@ -281,6 +377,40 @@
 };
 
 &sysgpio {
+       hdmi_pins: hdmi-0 {
+               hdmi-cec-pins {
+                       pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
+                                            GPOEN_SYS_HDMI_CEC_SDA,
+                                            GPI_SYS_HDMI_CEC_SDA)>;
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               hdmi-hpd-pins {
+                       pinmux = <GPIOMUX(15, GPOUT_HIGH,
+                                            GPOEN_ENABLE,
+                                            GPI_SYS_HDMI_HPD)>;
+                       input-enable;
+                       bias-disable; /* external pull-up */
+               };
+
+               hdmi-scl-pins {
+                       pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
+                                            GPOEN_SYS_HDMI_DDC_SCL,
+                                            GPI_SYS_HDMI_DDC_SCL)>;
+                       input-enable;
+                       bias-pull-up;
+               };
+
+               hdmi-sda-pins {
+                       pinmux = <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
+                                            GPOEN_SYS_HDMI_DDC_SDA,
+                                            GPI_SYS_HDMI_DDC_SDA)>;
+                       input-enable;
+                       bias-pull-up;
+               };
+       };
+
        i2c0_pins: i2c0-0 {
                i2c-pins {
                        pinmux = <GPIOMUX(57, GPOUT_LOW,
@@ -531,3 +661,7 @@
 &U74_4 {
        cpu-supply = <&vdd_cpu>;
 };
+
+&voutcrg {
+       status = "okay";
+};

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index e85464c..748c096 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -329,6 +329,24 @@
                #clock-cells = <0>;
        };
 
+       display: display-subsystem {
+               compatible = "starfive,display-subsystem";
+
+               clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>,
+                       <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
+                       <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
+                       <&voutcrg JH7110_VOUTCLK_DC8200_AHB>;
+               clock-names = "noc_bus", "dc_core", "axi_core", "ahb";
+               resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
+                        <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
+                        <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
+               reset-names = "axi","ahb", "core";
+       };
+
+       dsi_encoder: dsi_encoder {
+               compatible = "starfive,dsi-encoder";
+               starfive,syscon = <&vout_syscon 0x8 0x08>;
+       };
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
@@ -1028,6 +1046,37 @@
                        power-domains = <&pwrc JH7110_PD_ISP>;
                };
 
+               dc8200: lcd-controller@29400000 {
+                       compatible = "starfive,jh7110-dc8200";
+                       reg = <0x0 0x29400000 0x0 0x100>,
+                             <0x0 0x29400800 0x0 0x2000>;
+                       interrupts = <95>;
+                       clocks = <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
+                               <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>,
+                               <&hdmitx0_pixelclk>,
+                               <&voutcrg JH7110_VOUTCLK_DC8200_PIX>;
+                       clock-names = "channel0", "channel1",
+                                     "hdmi_tx", "dc_parent";
+               };
+
+               hdmi: hdmi@29590000 {
+                       compatible = "starfive,jh7110-inno-hdmi";
+                       reg = <0x0 0x29590000 0x0 0x4000>;
+                       interrupts = <99>;
+
+                       clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+                                <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+                                <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>;
+                       clock-names = "sysclk", "mclk", "bclk";
+                       resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+                       #sound-dai-cells = <0>;
+               };
+
+               vout_syscon: syscon@295b0000 {
+                       compatible = "starfive,jh7110-vout-syscon", "syscon";
+                       reg = <0 0x295b0000 0 0x90>;
+               };
+
                voutcrg: clock-controller@295c0000 {
                        compatible = "starfive,jh7110-voutcrg";
                        reg = <0x0 0x295c0000 0x0 0x10000>;