intel: genxml: add preemption control instructions

Helpful to debug kernel workaround batchbuffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index aeb9966..bd914ad 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2824,6 +2824,13 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ca0e78..cb32126 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2788,6 +2788,13 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 71626c1..28fbdfd 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2509,6 +2509,12 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index c32f2c3..0912b6f 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2752,6 +2752,12 @@
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
   </instruction>
 
+  <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+    <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+    <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+    <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+  </instruction>
+
   <instruction name="MI_ATOMIC" bias="2" length="3">
     <field name="Command Type" start="29" end="31" type="uint" default="0"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>