///
/// G_BRCOND is a conditional branch to \p Dest. At the beginning of
/// legalization, \p Ty will be a single bit (s1). Targets with interesting
- /// flags registers may change this.
+ /// flags registers may change this. For a wider type, whether the branch is
+ /// taken must only depend on bit 0 (for now).
///
/// \pre setBasicBlock or setMI must have been called.
///
MI.eraseFromParent();
return Legalized;
}
+ case TargetOpcode::G_BRCOND: {
+ unsigned TstExt = MRI.createGenericVirtualRegister(WideSize);
+ MIRBuilder.buildAnyExtend(WideTy, TstExt, MI.getOperand(0).getReg());
+ MIRBuilder.buildBrCond(WideTy, TstExt, *MI.getOperand(1).getMBB());
+ MI.eraseFromParent();
+ return Legalized;
+ }
}
}
DefaultActions[TargetOpcode::G_ANYEXTEND] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
+ DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
+ DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
+
DefaultActions[TargetOpcode::G_ADD] = NarrowScalar;
+
+ DefaultActions[TargetOpcode::G_BRCOND] = WidenScalar;
}
void MachineLegalizer::computeTables() {
setAction({MemOp, 1, p0}, Legal);
}
+ // Constants
for (auto Ty : {s32, s64}) {
setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal);
setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
+ // Control-flow
setAction({G_BR, LLT::unsized()}, Legal);
+ setAction({G_BRCOND, s32}, Legal);
+ for (auto Ty : {s1, s8, s16})
+ setAction({G_BRCOND, Ty}, WidenScalar);
+ // Pointer-handling
setAction({G_FRAME_INDEX, p0}, Legal);
setAction({G_PTRTOINT, 0, s64}, Legal);
define void @test_simple() {
entry:
ret void
+ next:
+ ret void
}
...
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
; CHECK: %2(64) = G_INTTOPTR { p0, s64 } %1
%1(64) = G_PTRTOINT { s64, p0 } %0
%2(64) = G_INTTOPTR { p0, s64 } %1
+
+ ; CHECK: [[TST32:%[0-9]+]](32) = G_ANYEXTEND s32 %3
+ ; CHECK: G_BRCOND s32 [[TST32]], %bb.1.next
+ %3(1) = G_TRUNC { s1, s64 } %0
+ G_BRCOND s1 %3, %bb.1.next
+
+ bb.1.next:
...