sh_eth: use Gigabit register map for R7S72100

The register maps for the Gigabit controllers and the Ether one used on
RZ/A1  (AKA R7S72100) are identical except for GECMR which is only present
on the true GEther controllers.  We no longer use the register map arrays
to determine if a given register exists,  and have added the GECMR flag to
the 'struct sh_eth_cpu_data' in the previous patch, so we're ready to drop
the R7S72100 specific register map -- this saves 216 bytes of object code
(ARM gcc 4.8.5).

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 7659b4d..8ed73f4 100644 (file)
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -142,69 +142,6 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
        [FWALCR1]       = 0x00b4,
 };
 
-static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
-       SH_ETH_OFFSET_DEFAULTS,
-
-       [EDSR]          = 0x0000,
-       [EDMR]          = 0x0400,
-       [EDTRR]         = 0x0408,
-       [EDRRR]         = 0x0410,
-       [EESR]          = 0x0428,
-       [EESIPR]        = 0x0430,
-       [TDLAR]         = 0x0010,
-       [TDFAR]         = 0x0014,
-       [TDFXR]         = 0x0018,
-       [TDFFR]         = 0x001c,
-       [RDLAR]         = 0x0030,
-       [RDFAR]         = 0x0034,
-       [RDFXR]         = 0x0038,
-       [RDFFR]         = 0x003c,
-       [TRSCER]        = 0x0438,
-       [RMFCR]         = 0x0440,
-       [TFTR]          = 0x0448,
-       [FDR]           = 0x0450,
-       [RMCR]          = 0x0458,
-       [RPADIR]        = 0x0460,
-       [FCFTR]         = 0x0468,
-       [CSMR]          = 0x04E4,
-
-       [ECMR]          = 0x0500,
-       [RFLR]          = 0x0508,
-       [ECSR]          = 0x0510,
-       [ECSIPR]        = 0x0518,
-       [PIR]           = 0x0520,
-       [APR]           = 0x0554,
-       [MPR]           = 0x0558,
-       [PFTCR]         = 0x055c,
-       [PFRCR]         = 0x0560,
-       [TPAUSER]       = 0x0564,
-       [MAHR]          = 0x05c0,
-       [MALR]          = 0x05c8,
-       [CEFCR]         = 0x0740,
-       [FRECR]         = 0x0748,
-       [TSFRCR]        = 0x0750,
-       [TLFRCR]        = 0x0758,
-       [RFCR]          = 0x0760,
-       [MAFCR]         = 0x0778,
-
-       [ARSTR]         = 0x0000,
-       [TSU_CTRST]     = 0x0004,
-       [TSU_FWSLC]     = 0x0038,
-       [TSU_VTAG0]     = 0x0058,
-       [TSU_ADSBSY]    = 0x0060,
-       [TSU_TEN]       = 0x0064,
-       [TSU_POST1]     = 0x0070,
-       [TSU_POST2]     = 0x0074,
-       [TSU_POST3]     = 0x0078,
-       [TSU_POST4]     = 0x007c,
-       [TSU_ADRH0]     = 0x0100,
-
-       [TXNLCR0]       = 0x0080,
-       [TXALCR0]       = 0x0084,
-       [RXNLCR0]       = 0x0088,
-       [RXALCR0]       = 0x008C,
-};
-
 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
        SH_ETH_OFFSET_DEFAULTS,
 
@@ -593,7 +530,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
        .chip_reset     = sh_eth_chip_reset,
        .set_duplex     = sh_eth_set_duplex,
 
-       .register_type  = SH_ETH_REG_FAST_RZ,
+       .register_type  = SH_ETH_REG_GIGABIT,
 
        .edtrr_trns     = EDTRR_TRNS_GETHER,
        .ecsr_value     = ECSR_ICD,
@@ -3139,9 +3076,6 @@ static const u16 *sh_eth_get_register_offset(int register_type)
        case SH_ETH_REG_GIGABIT:
                reg_offset = sh_eth_offset_gigabit;
                break;
-       case SH_ETH_REG_FAST_RZ:
-               reg_offset = sh_eth_offset_fast_rz;
-               break;
        case SH_ETH_REG_FAST_RCAR:
                reg_offset = sh_eth_offset_fast_rcar;
                break;

diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index 621a7d4..c1b3751 100644 (file)
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -145,7 +145,6 @@ enum {
 
 enum {
        SH_ETH_REG_GIGABIT,
-       SH_ETH_REG_FAST_RZ,
        SH_ETH_REG_FAST_RCAR,
        SH_ETH_REG_FAST_SH4,
        SH_ETH_REG_FAST_SH3_SH2