drm/i915: Read DRRS MSA timing delay from VBT

VBT hsa a field for the MSA timing delay, which supposedly
should be used with DRRS. Extract the data from the VBT.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220310004802.16310-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a559a19..93dc32f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -888,6 +888,9 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
                        i915->vbt.edp.low_vswing = vswing == 0;
                }
        }
+
+       i915->vbt.edp.drrs_msa_timing_delay =
+               (edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
 }
 
 static void

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 29cc6f7..6b22d46 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -356,10 +356,11 @@ struct intel_vbt_data {
                int lanes;
                int preemphasis;
                int vswing;
-               bool low_vswing;
-               bool initialized;
                int bpp;
                struct edp_power_seq pps;
+               u8 drrs_msa_timing_delay;
+               bool low_vswing;
+               bool initialized;
                bool hobl;
        } edp;