arm64: dts: rockchip: add powerdomains to rk3368

Add the core io-domain node for rk3368.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210925090405.2601792-3-heiko@sntech.de

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 4217897..79ee687 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3368-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/thermal/thermal.h>
 
@@ -615,6 +616,115 @@
                status = "disabled";
        };
 
+       pmu: power-management@ff730000 {
+               compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
+               reg = <0x0 0xff730000 0x0 0x1000>;
+
+               power: power-controller {
+                       compatible = "rockchip,rk3368-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       /*
+                        * Note: Although SCLK_* are the working clocks
+                        * of device without including on the NOC, needed for
+                        * synchronous reset.
+                        *
+                        * The clocks on the which NOC:
+                        * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+                        * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+                        * ACLK_RGA is on ACLK_RGA_NIU.
+                        * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+                        *
+                        * Which clock are device clocks:
+                        *      clocks          devices
+                        *      *_IEP           IEP:Image Enhancement Processor
+                        *      *_ISP           ISP:Image Signal Processing
+                        *      *_VIP           VIP:Video Input Processor
+                        *      *_VOP*          VOP:Visual Output Processor
+                        *      *_RGA           RGA
+                        *      *_EDP*          EDP
+                        *      *_DPHY*         LVDS
+                        *      *_HDMI          HDMI
+                        *      *_MIPI_*        MIPI
+                        */
+                       power-domain@RK3368_PD_VIO {
+                               reg = <RK3368_PD_VIO>;
+                               clocks = <&cru ACLK_IEP>,
+                                        <&cru ACLK_ISP>,
+                                        <&cru ACLK_VIP>,
+                                        <&cru ACLK_RGA>,
+                                        <&cru ACLK_VOP>,
+                                        <&cru ACLK_VOP_IEP>,
+                                        <&cru DCLK_VOP>,
+                                        <&cru HCLK_IEP>,
+                                        <&cru HCLK_ISP>,
+                                        <&cru HCLK_RGA>,
+                                        <&cru HCLK_VIP>,
+                                        <&cru HCLK_VOP>,
+                                        <&cru HCLK_VIO_HDCPMMU>,
+                                        <&cru PCLK_EDP_CTRL>,
+                                        <&cru PCLK_HDMI_CTRL>,
+                                        <&cru PCLK_HDCP>,
+                                        <&cru PCLK_ISP>,
+                                        <&cru PCLK_VIP>,
+                                        <&cru PCLK_DPHYRX>,
+                                        <&cru PCLK_DPHYTX0>,
+                                        <&cru PCLK_MIPI_CSI>,
+                                        <&cru PCLK_MIPI_DSI0>,
+                                        <&cru SCLK_VOP0_PWM>,
+                                        <&cru SCLK_EDP_24M>,
+                                        <&cru SCLK_EDP>,
+                                        <&cru SCLK_HDCP>,
+                                        <&cru SCLK_ISP>,
+                                        <&cru SCLK_RGA>,
+                                        <&cru SCLK_HDMI_CEC>,
+                                        <&cru SCLK_HDMI_HDCP>;
+                               pm_qos = <&qos_iep>,
+                                        <&qos_isp_r0>,
+                                        <&qos_isp_r1>,
+                                        <&qos_isp_w0>,
+                                        <&qos_isp_w1>,
+                                        <&qos_vip>,
+                                        <&qos_vop>,
+                                        <&qos_rga_r>,
+                                        <&qos_rga_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       /*
+                        * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+                        * (video endecoder & decoder) clocks that on the
+                        * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+                        */
+                       power-domain@RK3368_PD_VIDEO {
+                               reg = <RK3368_PD_VIDEO>;
+                               clocks = <&cru ACLK_VIDEO>,
+                                        <&cru HCLK_VIDEO>,
+                                        <&cru SCLK_HEVC_CABAC>,
+                                        <&cru SCLK_HEVC_CORE>;
+                               pm_qos = <&qos_hevc_r>,
+                                        <&qos_vpu_r>,
+                                        <&qos_vpu_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       /*
+                        * Note: ACLK_GPU is the GPU clock,
+                        * and on the ACLK_GPU_NIU (NOC).
+                        */
+                       power-domain@RK3368_PD_GPU_1 {
+                               reg = <RK3368_PD_GPU_1>;
+                               clocks = <&cru ACLK_GPU_CFG>,
+                                        <&cru ACLK_GPU_MEM>,
+                                        <&cru SCLK_GPU_CORE>;
+                               pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+       };
+
        pmugrf: syscon@ff738000 {
                compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
                reg = <0x0 0xff738000 0x0 0x1000>;
@@ -711,6 +821,7 @@
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3368_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -723,6 +834,7 @@
                clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
                clock-names = "aclk", "iface";
                #iommu-cells = <0>;
+               power-domains = <&power RK3368_PD_VIO>;
                rockchip,disable-mmu-reset;
                status = "disabled";
        };
@@ -733,6 +845,7 @@
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3368_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -759,6 +872,71 @@
                status = "disabled";
        };
 
+       qos_iep: qos@ffad0000 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0000 0x0 0x20>;
+       };
+
+       qos_isp_r0: qos@ffad0080 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0080 0x0 0x20>;
+       };
+
+       qos_isp_r1: qos@ffad0100 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0100 0x0 0x20>;
+       };
+
+       qos_isp_w0: qos@ffad0180 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0180 0x0 0x20>;
+       };
+
+       qos_isp_w1: qos@ffad0200 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0200 0x0 0x20>;
+       };
+
+       qos_vip: qos@ffad0280 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0280 0x0 0x20>;
+       };
+
+       qos_vop: qos@ffad0300 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0300 0x0 0x20>;
+       };
+
+       qos_rga_r: qos@ffad0380 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0380 0x0 0x20>;
+       };
+
+       qos_rga_w: qos@ffad0400 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffad0400 0x0 0x20>;
+       };
+
+       qos_hevc_r: qos@ffae0000 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffae0000 0x0 0x20>;
+       };
+
+       qos_vpu_r: qos@ffae0100 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffae0100 0x0 0x20>;
+       };
+
+       qos_vpu_w: qos@ffae0180 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffae0180 0x0 0x20>;
+       };
+
+       qos_gpu: qos@ffaf0000 {
+               compatible = "rockchip,rk3368-qos", "syscon";
+               reg = <0x0 0xffaf0000 0x0 0x20>;
+       };
+
        efuse256: efuse@ffb00000 {
                compatible = "rockchip,rk3368-efuse";
                reg = <0x0 0xffb00000 0x0 0x20>;