intel: enable L3 cache

Set GEN7_MOCS_L3_ON everywhere.

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 6a5e6a4..1fa9949 100644 (file)
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -1180,6 +1180,8 @@ void cmd_batch_state_base_address(struct intel_cmd *cmd)
     const uint8_t cmd_len = 10;
     const uint32_t dw0 = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) |
                          (cmd_len - 2);
+    const uint32_t mocs = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
+        (GEN7_MOCS_L3_ON << 8 | GEN7_MOCS_L3_ON << 4) : 0;
     uint32_t pos;
     uint32_t *dw;
 
@@ -1189,7 +1191,7 @@ void cmd_batch_state_base_address(struct intel_cmd *cmd)
 
     dw[0] = dw0;
     /* start offsets */
-    dw[1] = 1;
+    dw[1] = mocs | 1;
     dw[2] = 1;
     dw[3] = 1;
     dw[4] = 1;
@@ -1664,8 +1666,10 @@ static void gen6_3DSTATE_VERTEX_BUFFERS(struct intel_cmd *cmd)
         dw[0] = i << GEN6_VB_STATE_DW0_INDEX__SHIFT |
                 pipeline->vb[i].strideInBytes;
 
-        if (cmd_gen(cmd) >= INTEL_GEN(7))
-            dw[0] |= GEN7_VB_STATE_DW0_ADDR_MODIFIED;
+        if (cmd_gen(cmd) >= INTEL_GEN(7)) {
+            dw[0] |= GEN7_MOCS_L3_ON << GEN6_VB_STATE_DW0_MOCS__SHIFT |
+                     GEN7_VB_STATE_DW0_ADDR_MODIFIED;
+        }
 
         switch (pipeline->vb[i].stepRate) {
         case XGL_VERTEX_INPUT_STEP_RATE_VERTEX:
@@ -2433,7 +2437,7 @@ static void gen6_meta_vs(struct intel_cmd *cmd)
         dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS) | (7 - 2);
         dw[1] = 1 << GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT;
         dw[2] = 0;
-        dw[3] = offset;
+        dw[3] = offset | GEN7_MOCS_L3_ON;
         dw[4] = 0;
         dw[5] = 0;
         dw[6] = 0;
@@ -2861,7 +2865,7 @@ static void gen7_meta_ps(struct intel_cmd *cmd)
     dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) | (7 - 2);
     dw[1] = 1 << GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT;
     dw[2] = 0;
-    dw[3] = offset;
+    dw[3] = offset | GEN7_MOCS_L3_ON;
     dw[4] = 0;
     dw[5] = 0;
     dw[6] = 0;

diff --git a/icd/intel/view.c b/icd/intel/view.c
index 8f746ba..9fda59b 100644 (file)
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -187,7 +187,7 @@ static void surface_state_buf_gen7(const struct intel_gpu *gpu,
            pitch;
 
    dw[4] = 0;
-   dw[5] = 0;
+   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT;
 
    dw[6] = 0;
    dw[7] = 0;
@@ -431,7 +431,8 @@ static void surface_state_tex_gen7(const struct intel_gpu *gpu,
    else
       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
 
-   dw[5] = (first_level) << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
+   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT |
+           (first_level) << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
            lod;
 
    dw[6] = 0;
@@ -977,7 +978,8 @@ static void ds_view_init(struct intel_ds_view *view,
             info.lod;
 
       dw4 = (info.depth - 1) << 21 |
-            info.first_layer << 10;
+            info.first_layer << 10 |
+            GEN7_MOCS_L3_ON;
 
       dw5 = 0;
 
@@ -1025,6 +1027,8 @@ static void ds_view_init(struct intel_ds_view *view,
       dw[6] = info.stencil.stride - 1;
       dw[7] = img->s8_offset;
 
+      if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
+         dw[6] |= GEN7_MOCS_L3_ON << GEN6_STENCIL_DW1_MOCS__SHIFT;
       if (intel_gpu_gen(gpu) >= INTEL_GEN(7.5))
          dw[6] |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
    }
@@ -1037,6 +1041,9 @@ static void ds_view_init(struct intel_ds_view *view,
    if (info.hiz.stride) {
       dw[8] = info.hiz.stride - 1;
       dw[9] = img->aux_offset;
+
+      if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
+         dw[8] |= GEN7_MOCS_L3_ON << GEN6_HIZ_DW1_MOCS__SHIFT;
    }
    else {
       dw[8] = 0;