* config/epiphany/epiphany.opt (mfp-iarith): New option.

        * config/epiphany/epiphgany.md (addsi3): Check for TARGET_FP_IARITH.
        (subsi3, iadd, isub): Rename to ..
        (subsi3_i, iadd_i, isub_i): .. This.
        (subsi3, iadd, isub): New define_expands.

        * config/epiphany/epiphgany.md (attribute type): Add v2fp.
        (attribute fp_mode): Test for v2fp.
        (<float_operation:insn_opname>v2sf3_i): Change type to v2fp.
        * config/epiphany/epiphgany-sched.md (fp_arith_nearest, fp_arith_trunc):
        Combine to ..
        (fp_arith): .. this.
        (v2fp_arith): New insn reservation.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@193896 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ef32e39..35277bc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -6,6 +6,20 @@
        * config/epiphany/epiphany.c (REG_OK_FOR_BASE_P): Don't force a
        misaligned stack address to reg+index.
 
+       * config/epiphany/epiphany.opt (mfp-iarith): New option.
+       * config/epiphany/epiphgany.md (addsi3): Check for TARGET_FP_IARITH.
+       (subsi3, iadd, isub): Rename to ..
+       (subsi3_i, iadd_i, isub_i): .. This.
+       (subsi3, iadd, isub): New define_expands.
+
+       * config/epiphany/epiphgany.md (attribute type): Add v2fp.
+       (attribute fp_mode): Test for v2fp.
+       (<float_operation:insn_opname>v2sf3_i): Change type to v2fp.
+       * config/epiphany/epiphgany-sched.md (fp_arith_nearest, fp_arith_trunc):
+       Combine to ..
+       (fp_arith): .. this. 
+       (v2fp_arith): New insn reservation.
+
 2012-11-28  Oleg Raikhman  <oleg@adapteva.com>
 
        * config/epiphany/epiphany.h (ASM_OUTPUT_ALIGN_WITH_NOP): Define.

diff --git a/gcc/config/epiphany/epiphany-sched.md b/gcc/config/epiphany/epiphany-sched.md
index a2420a5..4d425bb 100644 (file)
--- a/gcc/config/epiphany/epiphany-sched.md
+++ b/gcc/config/epiphany/epiphany-sched.md
@@ -61,7 +61,7 @@
        (eq_attr "length" "4"))
   "issue,int")
 
-; anything but fp / fp_int has a bypass
+; anything but fp / fp_int / v2fp has a bypass
 (define_bypass 1 "simple_arith" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
 
 (define_insn_reservation "simple_arith_2" 2
@@ -84,7 +84,7 @@
        (eq_attr "type" "load"))
   "issue,int")
 
-; anything but fp / fp_int has a bypass
+; anything but fp / fp_int / v2fp has a bypass
 (define_bypass 2 "load" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
 
 (define_insn_reservation "store" 1
@@ -119,17 +119,20 @@
        (eq_attr "type" "flow"))
   "d_lock")
 \f
-(define_insn_reservation "fp_arith_trunc"  3
+(define_insn_reservation "fp_arith"  5
   (and (eq_attr "pipe_model" "epiphany")
-       (and (eq_attr "type" "fp,fp_int")
-           (eq_attr "rounding" "trunc")))
+       (eq_attr "type" "fp,fp_int"))
   "issue,F0")
 
-(define_insn_reservation "fp_arith_nearest"  5
-  (and (eq_attr "pipe_model" "epiphany")
-       (and (eq_attr "type" "fp,fp_int")
-           (eq_attr "rounding" "nearest")))
-  "issue,F0")
+(define_bypass 4 "fp_arith" "store")
 
-(define_bypass 2 "fp_arith_trunc" "store")
-(define_bypass 4 "fp_arith_nearest" "store")
+; There are two main consumers for v2fp:
+; - other v2fp operation - in that case, the latencies can dovetail to
+;   save one cycle of latency.
+; - 64 bit store operations - we need both registers, but OTOH the latency is
+; one lower to start with.
+; of the bypass saving one cyles then.
+(define_insn_reservation "v2fp_arith"  5
+  (and (eq_attr "pipe_model" "epiphany")
+       (eq_attr "type" "v2fp"))
+  "issue,issue+F0,F0")

diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md
index d0cbcc4..3a05a2a 100644 (file)
--- a/gcc/config/epiphany/epiphany.md
+++ b/gcc/config/epiphany/epiphany.md
@@ -57,7 +57,7 @@
 ;; Insn type.  Used to default other attribute values.
 
 (define_attr "type"
-  "move,load,store,cmove,unary,compare,shift,mul,uncond_branch,branch,call,fp,fp_int,misc,sfunc,fp_sfunc,flow"
+  "move,load,store,cmove,unary,compare,shift,mul,uncond_branch,branch,call,fp,fp_int,v2fp,misc,sfunc,fp_sfunc,flow"
   (const_string "misc"))
 
 ;; Length (in # bytes)
@@ -79,7 +79,7 @@
        (const_string "trunc")))
 
 (define_attr "fp_mode" "round_unknown,round_nearest,round_trunc,int,caller,none"
-  (cond [(eq_attr "type" "fp,fp_sfunc")
+  (cond [(eq_attr "type" "fp,v2fp,fp_sfunc")
         (symbol_ref "(enum attr_fp_mode) epiphany_normal_fp_rounding")
         (eq_attr "type" "call")
         (symbol_ref "(enum attr_fp_mode) epiphany_normal_fp_mode")
@@ -414,6 +414,8 @@
 {
   if (reload_in_progress || reload_completed)
     emit_insn (gen_addsi3_r (operands[0], operands[1], operands[2]));
+  else if (TARGET_FP_IARITH && add_reg_operand (operands[2], SImode))
+    emit_insn (gen_iadd (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_addsi3_i (operands[0], operands[1], operands[2]));
   DONE;
@@ -542,7 +544,23 @@
                                (plus:SI (match_dup 0) (match_dup 1)))))]
   "")
 
-(define_insn "subsi3"
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "gpr_operand" "")
+       (plus:SI (match_operand:SI 1 "add_reg_operand" "")
+                (match_operand:SI 2 "arith_operand" "")))]
+  ""
+  "
+{
+  gcc_assert (!reload_in_progress && !reload_completed);
+
+  if (TARGET_FP_IARITH)
+    emit_insn (gen_isub (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_subsi3_i (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_insn "subsi3_i"
   [(set (match_operand:SI 0 "gpr_operand" "=r")
        (minus:SI (match_operand:SI 1 "add_reg_operand" "r")
                  (match_operand:SI 2 "arith_operand" "rL")))
@@ -933,7 +951,7 @@
 
       op1si = simplify_gen_subreg (SImode, operands[1], SFmode, 0);
       emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
-      emit_insn (gen_subsi3 (tmp, op1si, bit31));
+      emit_insn (gen_subsi3_i (tmp, op1si, bit31));
       emit_insn (gen_ashlsi3 (tmp, tmp, GEN_INT (8)));
       emit_insn (gen_cmpsi_cc_insn (op1si, limit));
       emit_insn (gen_movsicc (operands[0], cmp, tmp, operands[0]));
@@ -962,7 +980,14 @@
   DONE;
 })
 
-(define_insn "*iadd"
+(define_expand "iadd"
+  [(parallel
+     [(set (match_operand:SF 0 "gpr_operand" "")
+          (plus:SI (match_operand:SF 1 "gpr_operand" "")
+                   (match_operand:SF 2 "gpr_operand" "")))
+      (clobber (reg:CC_FP CCFP_REGNUM))])])
+
+(define_insn "*iadd_i"
   [(match_parallel 3 "float_operation"
      [(set (match_operand:SI 0 "gpr_operand" "=r")
           (plus:SI (match_operand:SI 1 "gpr_operand" "%r")
@@ -972,7 +997,14 @@
   "iadd %0, %1, %2"
   [(set_attr "type" "fp_int")])
 
-(define_insn "*isub"
+(define_expand "isub"
+  [(parallel
+     [(set (match_operand:SF 0 "gpr_operand" "")
+          (minus:SI (match_operand:SF 1 "gpr_operand" "")
+                    (match_operand:SF 2 "gpr_operand" "")))
+      (clobber (reg:CC_FP CCFP_REGNUM))])])
+
+(define_insn "*isub_i"
   [(match_parallel 3 "float_operation"
      [(set (match_operand:SI 0 "gpr_operand" "=r")
           (minus:SI (match_operand:SI 1 "gpr_operand" "r")
@@ -2309,7 +2341,7 @@
   operands[11] = XVECEXP (operands[3], 0, XVECLEN (operands[3], 0) - 1);
 }
   [(set_attr "length" "8")
-   (set_attr "type" "fp")])
+   (set_attr "type" "v2fp")])
 
 (define_expand "mul<mode>3"
   [(parallel

diff --git a/gcc/config/epiphany/epiphany.opt b/gcc/config/epiphany/epiphany.opt
index 613bb98..cb3a4c7 100644 (file)
--- a/gcc/config/epiphany/epiphany.opt
+++ b/gcc/config/epiphany/epiphany.opt
@@ -127,6 +127,10 @@ msplit-vecmove-early
 Target Mask(SPLIT_VECMOVE_EARLY)
 Split unaligned 8 byte vector moves before post-modify address generation.
 
+mfp-iarith
+Target Mask(FP_IARITH)
+Use the floating point unit for integer add/subtract.
+
 m1reg-
 Target RejectNegative Joined Var(epiphany_m1reg) Enum(m1reg) Init(-1)
 Set register to hold -1.