}
+define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpeqr_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.i32 eq, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp eq <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpner_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.i32 ne, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp ne <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpsltr_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vdup.32 q2, r0
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.s32 gt, q2, q1
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp slt <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpsgtr_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.s32 gt, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp sgt <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpsler_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vdup.32 q2, r0
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.s32 ge, q2, q1
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp sle <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpsger_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.s32 ge, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp sge <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpultr_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vdup.32 q2, r0
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.u32 hi, q2, q1
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp ult <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpugtr_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.u32 hi, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp ugt <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpuler_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vdup.32 q2, r0
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.u32 cs, q2, q1
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp ule <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECK-LABEL: cmpuger_v4i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i32 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.u32 cs, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %a, zeroinitializer
+ %i = insertelement <4 x i32> undef, i32 %c, i32 0
+ %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
+ %c2 = icmp uge <4 x i32> %b, %sp
+ %o = and <4 x i1> %c1, %c2
+ %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
ret <8 x i16> %s
}
+define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {
+; CHECK-LABEL: cmpeqr_v8i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i16 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.i16 eq, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <8 x i16> %a, zeroinitializer
+ %i = insertelement <8 x i16> undef, i16 %c, i32 0
+ %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
+ %c2 = icmp eq <8 x i16> %b, %sp
+ %o = and <8 x i1> %c1, %c2
+ %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
+ ret <8 x i16> %s
+}
+
define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: cmpeqz_v16i1:
ret <16 x i8> %s
}
+define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {
+; CHECK-LABEL: cmpeqr_v16i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vcmp.i8 eq, q0, zr
+; CHECK-NEXT: vpst
+; CHECK-NEXT: vcmpt.i8 eq, q1, r0
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <16 x i8> %a, zeroinitializer
+ %i = insertelement <16 x i8> undef, i8 %c, i32 0
+ %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
+ %c2 = icmp eq <16 x i8> %b, %sp
+ %o = and <16 x i1> %c1, %c2
+ %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
+ ret <16 x i8> %s
+}
+
define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmpeqz_v2i1:
ret <2 x i64> %s
}
-
+define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {
+; CHECK-LABEL: cmpeqr_v2i1:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: vmov r3, s4
+; CHECK-NEXT: eors r2, r1
+; CHECK-NEXT: eors r3, r0
+; CHECK-NEXT: orrs r2, r3
+; CHECK-NEXT: clz r2, r2
+; CHECK-NEXT: lsrs r2, r2, #5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r2, #-1
+; CHECK-NEXT: vmov.32 q2[0], r2
+; CHECK-NEXT: vmov.32 q2[1], r2
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: eors r1, r2
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: eors r0, r2
+; CHECK-NEXT: orrs r0, r1
+; CHECK-NEXT: vmov r1, s0
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsrs r0, r0, #5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r0, #-1
+; CHECK-NEXT: vmov.32 q2[2], r0
+; CHECK-NEXT: vmov.32 q2[3], r0
+; CHECK-NEXT: vmov r0, s1
+; CHECK-NEXT: orrs r0, r1
+; CHECK-NEXT: vmov r1, s2
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsrs r0, r0, #5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r0, #-1
+; CHECK-NEXT: vmov.32 q3[0], r0
+; CHECK-NEXT: vmov.32 q3[1], r0
+; CHECK-NEXT: vmov r0, s3
+; CHECK-NEXT: orrs r0, r1
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsrs r0, r0, #5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r0, #-1
+; CHECK-NEXT: vmov.32 q3[2], r0
+; CHECK-NEXT: vmov.32 q3[3], r0
+; CHECK-NEXT: vand q2, q3, q2
+; CHECK-NEXT: vbic q1, q1, q2
+; CHECK-NEXT: vand q0, q0, q2
+; CHECK-NEXT: vorr q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <2 x i64> %a, zeroinitializer
+ %i = insertelement <2 x i64> undef, i64 %c, i32 0
+ %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
+ %c2 = icmp eq <2 x i64> %b, %sp
+ %o = and <2 x i1> %c1, %c2
+ %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %s
+}
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
+; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vmrs r0, p0
; CHECK-MVEFP-NEXT: eors r0, r1
; CHECK-MVEFP-NEXT: vmsr p0, r0
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
+; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
+; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vmrs r0, p0
; CHECK-MVEFP-NEXT: eors r0, r1
; CHECK-MVEFP-NEXT: vmsr p0, r0
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
+; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr
entry:
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q3
+; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vmrs r0, p0
; CHECK-MVEFP-NEXT: eors r0, r1
; CHECK-MVEFP-NEXT: vmsr p0, r0
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q3
+; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry:
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q3
+; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vmrs r0, p0
; CHECK-MVEFP-NEXT: eors r0, r1
; CHECK-MVEFP-NEXT: vmsr p0, r0
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
; CHECK-MVEFP-NEXT: vpst
-; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q3
+; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr
entry: