mx6: ddr: allow 32 cycles for DQS gating calibration

The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.

Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7beb7ea..b15f376 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -347,6 +347,8 @@ int mmdc_do_dqs_calibration(void)
         * 16 before comparing read data.
         */
        setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+       if (sysinfo->dsize == 2)
+               setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
 
        /* Set bit 28 to start automatic read DQS gating calibration */
        setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
@@ -365,6 +367,11 @@ int mmdc_do_dqs_calibration(void)
        if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
                errors |= 2;
 
+       /* now disable mpdgctrl0[DG_CMP_CYC] */
+       clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+       if (sysinfo->dsize == 2)
+               clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
        /*
         * DQS gating absolute offset should be modified from
         * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to