net: macb: Set MDIO clock divisor for pclk higher than 160MHz

Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 14dfec4db8f9ee17b0a49b7a293708b16cad2a69..c1fc91c97cee4d619a57bfe4dfc536eaa66b377c 100644 (file)
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -692,6 +692,8 @@
 #define GEM_CLK_DIV48                          3
 #define GEM_CLK_DIV64                          4
 #define GEM_CLK_DIV96                          5
+#define GEM_CLK_DIV128                         6
+#define GEM_CLK_DIV224                         7
 
 /* Constants for MAN register */
 #define MACB_MAN_C22_SOF                       1

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index c4edd20c1c668f6163e118f8785b7dd82ffc2d2d..7698719b1909631e13f72edd91b5e44ee7c23a4f 100644 (file)
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -2640,8 +2640,12 @@ static u32 gem_mdc_clk_div(struct macb *bp)
                config = GEM_BF(CLK, GEM_CLK_DIV48);
        else if (pclk_hz <= 160000000)
                config = GEM_BF(CLK, GEM_CLK_DIV64);
-       else
+       else if (pclk_hz <= 240000000)
                config = GEM_BF(CLK, GEM_CLK_DIV96);
+       else if (pclk_hz <= 320000000)
+               config = GEM_BF(CLK, GEM_CLK_DIV128);
+       else
+               config = GEM_BF(CLK, GEM_CLK_DIV224);
 
        return config;
 }