#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/mt7621-clk.h>
/ {
#address-cells = <1>;
serial0 = &uartlite;
};
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <880000000>;
- };
-
- sysclock: sysclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* This is normally 1/4 of cpuclock */
- clock-frequency = <220000000>;
- };
-
- mmc_clock: mmc_clock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- };
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
#size-cells = <1>;
sysc: sysc@0 {
- compatible = "mtk,mt7621-sysc";
+ compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
};
wdt: wdt@100 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
resets = <&rstctrl 16>;
reset-names = "i2c";
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&sysc MT7621_CLK_I2S>;
+ clock-names = "i2s";
resets = <&rstctrl 17>;
reset-names = "i2s";
};
memc: memc@5000 {
- compatible = "mtk,mt7621-memc";
+ compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysclock>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART1>;
+ clock-names = "uart1";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_SPI>;
+ clock-names = "spi";
resets = <&rstctrl 18>;
reset-names = "spi";
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
+ clocks = <&sysc MT7621_CLK_GDMA>;
+ clock-names = "gdma";
resets = <&rstctrl 14>;
reset-names = "dma";
compatible = "mediatek,mt7621-hsdma";
reg = <0x7000 0x1000>;
+ clocks = <&sysc MT7621_CLK_HSDMA>;
+ clock-names = "hsdma";
resets = <&rstctrl 5>;
reset-names = "hsdma";
#reset-cells = <1>;
};
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
sdhci: sdhci@1E130000 {
status = "disabled";
pinctrl-0 = <&sdhci_pins>;
pinctrl-1 = <&sdhci_pins>;
- clocks = <&mmc_clock &mmc_clock>;
+ clocks = <&sysc MT7621_CLK_SHXC>,
+ <&sysc MT7621_CLK_50M>;
clock-names = "source", "hclk";
interrupt-parent = <&gic>;
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
clock-names = "sys_ck";
interrupt-parent = <&gic>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&cpuclock>;
+ clocks = <&sysc MT7621_CLK_CPU>;
};
};
0x1e003800 0x800>;
#address-cells = <1>;
#size-cells = <1>;
+
+ clocks = <&sysc MT7621_CLK_NAND>;
+ clock-names = "nand";
};
ethsys: syscon@1e000000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysclock>;
- clock-names = "ethif";
+ clocks = <&sysc MT7621_CLK_FE>,
+ <&sysc MT7621_CLK_ETH>;
+ clock-names = "fe", "ethif";
#address-cells = <1>;
#size-cells = <0>;
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
reset-names = "pcie0", "pcie1", "pcie2";
- clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+ clocks = <&sysc MT7621_CLK_PCIE0>,
+ <&sysc MT7621_CLK_PCIE1>,
+ <&sysc MT7621_CLK_PCIE2>;
clock-names = "pcie0", "pcie1", "pcie2";
phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
phy-names = "pcie-phy0", "pcie-phy2";