arm64: dts: renesas: r8a779a0: Add DSI encoders

Provide the two MIPI DSI encoders on the V3U and connect them to the DU
accordingly.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20211130164311.2909616-2-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 8ac1a31..f89bcc6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -2290,12 +2290,14 @@
                                port@0 {
                                        reg = <0>;
                                        du_out_dsi0: endpoint {
+                                               remote-endpoint = <&dsi0_in>;
                                        };
                                };
 
                                port@1 {
                                        reg = <1>;
                                        du_out_dsi1: endpoint {
+                                               remote-endpoint = <&dsi1_in>;
                                        };
                                };
                        };
@@ -2633,6 +2635,62 @@
                        };
                };
 
+               dsi0: dsi-encoder@fed80000 {
+                       compatible = "renesas,r8a779a0-dsi-csi2-tx";
+                       reg = <0 0xfed80000 0 0x10000>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       clocks = <&cpg CPG_MOD 415>,
+                                <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+                                <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
+                       clock-names = "fck", "dsi", "pll";
+                       resets = <&cpg 415>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi0_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi0>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               dsi1: dsi-encoder@fed90000 {
+                       compatible = "renesas,r8a779a0-dsi-csi2-tx";
+                       reg = <0 0xfed90000 0 0x10000>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       clocks = <&cpg CPG_MOD 416>,
+                                <&cpg CPG_CORE R8A779A0_CLK_DSI>,
+                                <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
+                       clock-names = "fck", "dsi", "pll";
+                       resets = <&cpg 416>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi1_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi1>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;