audio:sn95031:Updating Audio PLL Power up sequence

BZ: 33301

CLKSTRT bit is enabled prior to the PLLEN bit,
it violates TI recommandation.

Set the CLKSTRT bit at the end of the power-up sequence.

Change-Id: I08fea0a4512435c38bf10d8f5bdb9aeffd98b2c7
Signed-off-by: KuldeepX Vyas <kuldeepx.vyas@intel.com>
Reviewed-on: http://android.intel.com:8080/46688
Reviewed-by: Babu, Ramesh <ramesh.babu@intel.com>
Reviewed-by: Abdullah, Omair M <omair.m.abdullah@intel.com>
Reviewed-by: Koul, Vinod <vinod.koul@intel.com>
Reviewed-by: Gupta, ArvindX K <arvindx.k.gupta@intel.com>
Reviewed-by: Hibare, PramodX <pramodx.hibare@intel.com>
Tested-by: Hibare, PramodX <pramodx.hibare@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/sound/soc/codecs/sn95031.c b/sound/soc/codecs/sn95031.c
index 6e5ec2d..9f138ff 100644 (file)
--- a/sound/soc/codecs/sn95031.c
+++ b/sound/soc/codecs/sn95031.c
@@ -79,13 +79,14 @@ void sn95031_configure_pll(struct snd_soc_codec *codec, int operation)
        struct sn95031_priv *sn95031_ctx;
        sn95031_ctx = snd_soc_codec_get_drvdata(codec);
 
+
        if (sn95031_ctx->pll_state == PLL_ENABLE_PENDING
                        && operation == SN95031_ENABLE_PLL) {
                pr_debug("setting PLL to 0x%x\n", sn95031_ctx->clk_src);
-               snd_soc_write(codec, SN95031_AUDPLLCTRL, 0x20);
-               udelay(1000);
                /* PLL takes few msec to stabilize
                Refer sec2.3 MFLD Audio Interface Doc-rev0.7 */
+               snd_soc_write(codec, SN95031_AUDPLLCTRL, 0);
+               udelay(1000);
                snd_soc_write(codec, SN95031_AUDPLLCTRL,
                                        (sn95031_ctx->clk_src)<<2);
                udelay(1000);
@@ -96,9 +97,9 @@ void sn95031_configure_pll(struct snd_soc_codec *codec, int operation)
                sn95031_ctx->pll_state = PLL_ENABLED;
        } else if (operation == SN95031_DISABLE_PLL) {
                pr_debug("disabling PLL\n");
+               snd_soc_write(codec, SN95031_AUDPLLCTRL, 0);
                sn95031_ctx->clk_src = SN95031_INVALID;
                sn95031_ctx->pll_state = PLL_DISABLED;
-               snd_soc_write(codec, SN95031_AUDPLLCTRL, 0);
        } else {
                pr_debug("PLL configure state: op=0x%x, state=0x%x\n",
                                operation, sn95031_ctx->pll_state);