iMX28: Add USB and USB PHY register definitions
authorMarek Vasut <marek.vasut@gmail.com>
Tue, 8 Nov 2011 23:18:25 +0000 (23:18 +0000)
committerStefano Babic <sbabic@denx.de>
Fri, 11 Nov 2011 10:36:58 +0000 (11:36 +0100)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
arch/arm/include/asm/arch-mx28/regs-usb.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx28/regs-usbphy.h [new file with mode: 0644]

diff --git a/arch/arm/include/asm/arch-mx28/regs-usb.h b/arch/arm/include/asm/arch-mx28/regs-usb.h
new file mode 100644 (file)
index 0000000..ea61de8
--- /dev/null
@@ -0,0 +1,178 @@
+/*
+ * Freescale i.MX28 USB OTG Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct mx28_usb_regs {
+       uint32_t                hw_usbctrl_id;                  /* 0x000 */
+       uint32_t                hw_usbctrl_hwgeneral;           /* 0x004 */
+       uint32_t                hw_usbctrl_hwhost;              /* 0x008 */
+       uint32_t                hw_usbctrl_hwdevice;            /* 0x00c */
+       uint32_t                hw_usbctrl_hwtxbuf;             /* 0x010 */
+       uint32_t                hw_usbctrl_hwrxbuf;             /* 0x014 */
+
+       uint32_t                reserved1[26];
+
+       uint32_t                hw_usbctrl_gptimer0ld;          /* 0x080 */
+       uint32_t                hw_usbctrl_gptimer0ctrl;        /* 0x084 */
+       uint32_t                hw_usbctrl_gptimer1ld;          /* 0x088 */
+       uint32_t                hw_usbctrl_gptimer1ctrl;        /* 0x08c */
+       uint32_t                hw_usbctrl_sbuscfg;             /* 0x090 */
+
+       uint32_t                reserved2[27];
+
+       uint32_t                hw_usbctrl_caplength;           /* 0x100 */
+       uint32_t                hw_usbctrl_hcsparams;           /* 0x104 */
+       uint32_t                hw_usbctrl_hccparams;           /* 0x108 */
+
+       uint32_t                reserved3[5];
+
+       uint32_t                hw_usbctrl_dciversion;          /* 0x120 */
+       uint32_t                hw_usbctrl_dccparams;           /* 0x124 */
+
+       uint32_t                reserved4[6];
+
+       uint32_t                hw_usbctrl_usbcmd;              /* 0x140 */
+       uint32_t                hw_usbctrl_usbsts;              /* 0x144 */
+       uint32_t                hw_usbctrl_usbintr;             /* 0x148 */
+       uint32_t                hw_usbctrl_frindex;             /* 0x14c */
+
+       uint32_t                reserved5;
+
+       union {
+               uint32_t        hw_usbctrl_periodiclistbase;    /* 0x154 */
+               uint32_t        hw_usbctrl_deviceaddr;          /* 0x154 */
+       };
+       union {
+               uint32_t        hw_usbctrl_asynclistaddr;       /* 0x158 */
+               uint32_t        hw_usbctrl_endpointlistaddr;    /* 0x158 */
+       };
+
+       uint32_t                hw_usbctrl_ttctrl;              /* 0x15c */
+       uint32_t                hw_usbctrl_burstsize;           /* 0x160 */
+       uint32_t                hw_usbctrl_txfilltuning;        /* 0x164 */
+
+       uint32_t                reserved6;
+
+       uint32_t                hw_usbctrl_ic_usb;              /* 0x16c */
+       uint32_t                hw_usbctrl_ulpi;                /* 0x170 */
+
+       uint32_t                reserved7;
+
+       uint32_t                hw_usbctrl_endptnak;            /* 0x178 */
+       uint32_t                hw_usbctrl_endptnaken;          /* 0x17c */
+
+       uint32_t                reserved8;
+
+       uint32_t                hw_usbctrl_portsc1;             /* 0x184 */
+
+       uint32_t                reserved9[7];
+
+       uint32_t                hw_usbctrl_otgsc;               /* 0x1a4 */
+       uint32_t                hw_usbctrl_usbmode;             /* 0x1a8 */
+       uint32_t                hw_usbctrl_endptsetupstat;      /* 0x1ac */
+       uint32_t                hw_usbctrl_endptprime;          /* 0x1b0 */
+       uint32_t                hw_usbctrl_endptflush;          /* 0x1b4 */
+       uint32_t                hw_usbctrl_endptstat;           /* 0x1b8 */
+       uint32_t                hw_usbctrl_endptcomplete;       /* 0x1bc */
+       uint32_t                hw_usbctrl_endptctrl0;          /* 0x1c0 */
+       uint32_t                hw_usbctrl_endptctrl1;          /* 0x1c4 */
+       uint32_t                hw_usbctrl_endptctrl2;          /* 0x1c8 */
+       uint32_t                hw_usbctrl_endptctrl3;          /* 0x1cc */
+       uint32_t                hw_usbctrl_endptctrl4;          /* 0x1d0 */
+       uint32_t                hw_usbctrl_endptctrl5;          /* 0x1d4 */
+       uint32_t                hw_usbctrl_endptctrl6;          /* 0x1d8 */
+       uint32_t                hw_usbctrl_endptctrl7;          /* 0x1dc */
+};
+
+#define        CLKCTRL_PLL0CTRL0_LFR_SEL_MASK          (0x3 << 28)
+
+#define        HW_USBCTRL_ID_CIVERSION_OFFSET          29
+#define        HW_USBCTRL_ID_CIVERSION_MASK            (0x7 << 29)
+#define        HW_USBCTRL_ID_VERSION_OFFSET            25
+#define        HW_USBCTRL_ID_VERSION_MASK              (0xf << 25)
+#define        HW_USBCTRL_ID_REVISION_OFFSET           21
+#define        HW_USBCTRL_ID_REVISION_MASK             (0xf << 21)
+#define        HW_USBCTRL_ID_TAG_OFFSET                16
+#define        HW_USBCTRL_ID_TAG_MASK                  (0x1f << 16)
+#define        HW_USBCTRL_ID_NID_OFFSET                8
+#define        HW_USBCTRL_ID_NID_MASK                  (0x3f << 8)
+#define        HW_USBCTRL_ID_ID_OFFSET                 0
+#define        HW_USBCTRL_ID_ID_MASK                   (0x3f << 0)
+
+#define        HW_USBCTRL_HWGENERAL_SM_OFFSET          9
+#define        HW_USBCTRL_HWGENERAL_SM_MASK            (0x3 << 9)
+#define        HW_USBCTRL_HWGENERAL_PHYM_OFFSET        6
+#define        HW_USBCTRL_HWGENERAL_PHYM_MASK          (0x7 << 6)
+#define        HW_USBCTRL_HWGENERAL_PHYW_OFFSET        4
+#define        HW_USBCTRL_HWGENERAL_PHYW_MASK          (0x3 << 4)
+#define        HW_USBCTRL_HWGENERAL_BWT                (1 << 3)
+#define        HW_USBCTRL_HWGENERAL_CLKC_OFFSET        1
+#define        HW_USBCTRL_HWGENERAL_CLKC_MASK          (0x3 << 1)
+#define        HW_USBCTRL_HWGENERAL_RT                 (1 << 0)
+
+#define        HW_USBCTRL_HWHOST_TTPER_OFFSET          24
+#define        HW_USBCTRL_HWHOST_TTPER_MASK            (0xff << 24)
+#define        HW_USBCTRL_HWHOST_TTASY_OFFSET          16
+#define        HW_USBCTRL_HWHOST_TTASY_MASK            (0xff << 19)
+#define        HW_USBCTRL_HWHOST_NPORT_OFFSET          1
+#define        HW_USBCTRL_HWHOST_NPORT_MASK            (0x7 << 1)
+#define        HW_USBCTRL_HWHOST_HC                    (1 << 0)
+
+#define        HW_USBCTRL_HWDEVICE_DEVEP_OFFSET        1
+#define        HW_USBCTRL_HWDEVICE_DEVEP_MASK          (0x1f << 1)
+#define        HW_USBCTRL_HWDEVICE_DC                  (1 << 0)
+
+#define        HW_USBCTRL_HWTXBUF_TXLCR                (1 << 31)
+#define        HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET     16
+#define        HW_USBCTRL_HWTXBUF_TXCHANADD_MASK       (0xff << 16)
+#define        HW_USBCTRL_HWTXBUF_TXADD_OFFSET         8
+#define        HW_USBCTRL_HWTXBUF_TXADD_MASK           (0xff << 8)
+#define        HW_USBCTRL_HWTXBUF_TXBURST_OFFSET       0
+#define        HW_USBCTRL_HWTXBUF_TXBURST_MASK         0xff
+
+#define        HW_USBCTRL_HWRXBUF_RXADD_OFFSET         8
+#define        HW_USBCTRL_HWRXBUF_RXADD_MASK           (0xff << 8)
+#define        HW_USBCTRL_HWRXBUF_RXBURST_OFFSET       0
+#define        HW_USBCTRL_HWRXBUF_RXBURST_MASK         0xff
+
+#define        HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET       0
+#define        HW_USBCTRL_GPTIMERLD_GPTLD_MASK         0xffffff
+
+#define        HW_USBCTRL_GPTIMERCTRL_GPTRUN           (1 << 31)
+#define        HW_USBCTRL_GPTIMERCTRL_GPTRST           (1 << 30)
+#define        HW_USBCTRL_GPTIMERCTRL_GPTMODE          (1 << 24)
+#define        HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET    0
+#define        HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK      0xffffff
+
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET      0
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_MASK        0x7
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR      0x0
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4     0x1
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8     0x2
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16    0x3
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4     0x5
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8     0x6
+#define        HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16    0x7
+
+#endif /* __REGS_USB_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h
new file mode 100644 (file)
index 0000000..e823e19
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * Freescale i.MX28 USB PHY Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+struct mx28_usbphy_regs {
+       mx28_reg(hw_usbphy_pwd)
+       mx28_reg(hw_usbphy_tx)
+       mx28_reg(hw_usbphy_rx)
+       mx28_reg(hw_usbphy_ctrl)
+       mx28_reg(hw_usbphy_status)
+       mx28_reg(hw_usbphy_debug)
+       mx28_reg(hw_usbphy_debug0_status)
+       mx28_reg(hw_usbphy_debug1)
+       mx28_reg(hw_usbphy_version)
+       mx28_reg(hw_usbphy_ip)
+};
+
+#define        USBPHY_PWD_RXPWDRX                              (1 << 20)
+#define        USBPHY_PWD_RXPWDDIFF                            (1 << 19)
+#define        USBPHY_PWD_RXPWD1PT1                            (1 << 18)
+#define        USBPHY_PWD_RXPWDENV                             (1 << 17)
+#define        USBPHY_PWD_TXPWDV2I                             (1 << 12)
+#define        USBPHY_PWD_TXPWDIBIAS                           (1 << 11)
+#define        USBPHY_PWD_TXPWDFS                              (1 << 10)
+
+#define        USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET             26
+#define        USBPHY_TX_USBPHY_TX_EDGECTRL_MASK               (0x7 << 26)
+#define        USBPHY_TX_USBPHY_TX_SYNC_INVERT                 (1 << 25)
+#define        USBPHY_TX_USBPHY_TX_SYNC_MUX                    (1 << 24)
+#define        USBPHY_TX_TXENCAL45DP                           (1 << 21)
+#define        USBPHY_TX_TXCAL45DP_OFFSET                      16
+#define        USBPHY_TX_TXCAL45DP_MASK                        (0xf << 16)
+#define        USBPHY_TX_TXENCAL45DM                           (1 << 13)
+#define        USBPHY_TX_TXCAL45DM_OFFSET                      8
+#define        USBPHY_TX_TXCAL45DM_MASK                        (0xf << 8)
+#define        USBPHY_TX_D_CAL_OFFSET                          0
+#define        USBPHY_TX_D_CAL_MASK                            0xf
+
+#define        USBPHY_RX_RXDBYPASS                             (1 << 22)
+#define        USBPHY_RX_DISCONADJ_OFFSET                      4
+#define        USBPHY_RX_DISCONADJ_MASK                        (0x7 << 4)
+#define        USBPHY_RX_ENVADJ_OFFSET                         0
+#define        USBPHY_RX_ENVADJ_MASK                           0x7
+
+#define        USBPHY_CTRL_SFTRST                              (1 << 31)
+#define        USBPHY_CTRL_CLKGATE                             (1 << 30)
+#define        USBPHY_CTRL_UTMI_SUSPENDM                       (1 << 29)
+#define        USBPHY_CTRL_HOST_FORCE_LS_SE0                   (1 << 28)
+#define        USBPHY_CTRL_ENAUTOSET_USBCLKS                   (1 << 26)
+#define        USBPHY_CTRL_ENAUTOCLR_USBCLKGATE                (1 << 25)
+#define        USBPHY_CTRL_FSDLL_RST_EN                        (1 << 24)
+#define        USBPHY_CTRL_ENVBUSCHG_WKUP                      (1 << 23)
+#define        USBPHY_CTRL_ENIDCHG_WKUP                        (1 << 22)
+#define        USBPHY_CTRL_ENDPDMCHG_WKUP                      (1 << 21)
+#define        USBPHY_CTRL_ENAUTOCLR_PHY_PWD                   (1 << 20)
+#define        USBPHY_CTRL_ENAUTOCLR_CLKGATE                   (1 << 19)
+#define        USBPHY_CTRL_ENAUTO_PWRON_PLL                    (1 << 18)
+#define        USBPHY_CTRL_WAKEUP_IRQ                          (1 << 17)
+#define        USBPHY_CTRL_ENIRQWAKEUP                         (1 << 16)
+#define        USBPHY_CTRL_ENUTMILEVEL3                        (1 << 15)
+#define        USBPHY_CTRL_ENUTMILEVEL2                        (1 << 14)
+#define        USBPHY_CTRL_DATA_ON_LRADC                       (1 << 13)
+#define        USBPHY_CTRL_DEVPLUGIN_IRQ                       (1 << 12)
+#define        USBPHY_CTRL_ENIRQDEVPLUGIN                      (1 << 11)
+#define        USBPHY_CTRL_RESUME_IRQ                          (1 << 10)
+#define        USBPHY_CTRL_ENIRQRESUMEDETECT                   (1 << 9)
+#define        USBPHY_CTRL_RESUMEIRQSTICKY                     (1 << 8)
+#define        USBPHY_CTRL_ENOTGIDDETECT                       (1 << 7)
+#define        USBPHY_CTRL_DEVPLUGIN_POLARITY                  (1 << 5)
+#define        USBPHY_CTRL_ENDEVPLUGINDETECT                   (1 << 4)
+#define        USBPHY_CTRL_HOSTDISCONDETECT_IRQ                (1 << 3)
+#define        USBPHY_CTRL_ENIRQHOSTDISCON                     (1 << 2)
+#define        USBPHY_CTRL_ENHOSTDISCONDETECT                  (1 << 1)
+
+#define        USBPHY_STATUS_RESUME_STATUS                     (1 << 10)
+#define        USBPHY_STATUS_OTGID_STATUS                      (1 << 8)
+#define        USBPHY_STATUS_DEVPLUGIN_STATUS                  (1 << 6)
+#define        USBPHY_STATUS_HOSTDISCONDETECT_STATUS           (1 << 3)
+
+#define        USBPHY_DEBUG_CLKGATE                            (1 << 30)
+#define        USBPHY_DEBUG_HOST_RESUME_DEBUG                  (1 << 29)
+#define        USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET          25
+#define        USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK            (0xf << 25)
+#define        USBPHY_DEBUG_ENSQUELCHRESET                     (1 << 24)
+#define        USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET           16
+#define        USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK             (0x1f << 16)
+#define        USBPHY_DEBUG_ENTX2RXCOUNT                       (1 << 12)
+#define        USBPHY_DEBUG_TX2RXCOUNT_OFFSET                  8
+#define        USBPHY_DEBUG_TX2RXCOUNT_MASK                    (0xf << 8)
+#define        USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET               4
+#define        USBPHY_DEBUG_ENHSTPULLDOWN_MASK                 (0x3 << 4)
+#define        USBPHY_DEBUG_HSTPULLDOWN_OFFSET                 2
+#define        USBPHY_DEBUG_HSTPULLDOWN_MASK                   (0x3 << 2)
+#define        USBPHY_DEBUG_DEBUG_INTERFACE_HOLD               (1 << 1)
+#define        USBPHY_DEBUG_OTGIDPIDLOCK                       (1 << 0)
+
+#define        USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET       26
+#define        USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK         (0x3f << 26)
+#define        USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET        16
+#define        USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK          (0x3ff << 16)
+#define        USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET           0
+#define        USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK             0xffff
+
+#define        USBPHY_DEBUG1_ENTAILADJVD_OFFSET                13
+#define        USBPHY_DEBUG1_ENTAILADJVD_MASK                  (0x3 << 13)
+#define        USBPHY_DEBUG1_ENTX2TX                           (1 << 12)
+#define        USBPHY_DEBUG1_DBG_ADDRESS_OFFSET                0
+#define        USBPHY_DEBUG1_DBG_ADDRESS_MASK                  0xf
+
+#define        USBPHY_VERSION_MAJOR_MASK                       (0xff << 24)
+#define        USBPHY_VERSION_MAJOR_OFFSET                     24
+#define        USBPHY_VERSION_MINOR_MASK                       (0xff << 16)
+#define        USBPHY_VERSION_MINOR_OFFSET                     16
+#define        USBPHY_VERSION_STEP_MASK                        0xffff
+#define        USBPHY_VERSION_STEP_OFFSET                      0
+
+#define        USBPHY_IP_DIV_SEL_OFFSET                        23
+#define        USBPHY_IP_DIV_SEL_MASK                          (0x3 << 23)
+#define        USBPHY_IP_LFR_SEL_OFFSET                        21
+#define        USBPHY_IP_LFR_SEL_MASK                          (0x3 << 21)
+#define        USBPHY_IP_CP_SEL_OFFSET                         19
+#define        USBPHY_IP_CP_SEL_MASK                           (0x3 << 19)
+#define        USBPHY_IP_TSTI_TX_DP                            (1 << 18)
+#define        USBPHY_IP_TSTI_TX_DM                            (1 << 17)
+#define        USBPHY_IP_ANALOG_TESTMODE                       (1 << 16)
+#define        USBPHY_IP_EN_USB_CLKS                           (1 << 2)
+#define        USBPHY_IP_PLL_LOCKED                            (1 << 1)
+#define        USBPHY_IP_PLL_POWER                             (1 << 0)
+
+#endif /* __REGS_USBPHY_H__ */