Merge branch kvm-arm64/wfxt into kvmarm-master/next

* kvm-arm64/wfxt:
  : .
  : Add support for the WFET/WFIT instructions that provide the same
  : service as WFE/WFI, only with a timeout.
  : .
  KVM: arm64: Expose the WFXT feature to guests
  KVM: arm64: Offer early resume for non-blocking WFxT instructions
  KVM: arm64: Handle blocking WFIT instruction
  KVM: arm64: Introduce kvm_counter_compute_delta() helper
  KVM: arm64: Simplify kvm_cpu_has_pending_timer()
  arm64: Use WFxT for __delay() when possible
  arm64: Add wfet()/wfit() helpers
  arm64: Add HWCAP advertising FEAT_WFXT
  arm64: Add RV and RN fields for ESR_ELx_WFx_ISS
  arm64: Expand ESR_ELx_WFx_ISS_TI to match its ARMv8.7 definition

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --cc Documentation/arm64/elf_hwcaps.rst
index f8d818e,af3ab52..3d116fb
--- 1/Documentation/arm64/elf_hwcaps.rst
--- 2/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@@ -264,39 -264,10 +264,43 @@@ HWCAP2_MTE
      Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
      by Documentation/arm64/memory-tagging-extension.rst.
  
 +HWCAP2_SME
 +
 +    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
 +    by Documentation/arm64/sme.rst.
 +
 +HWCAP2_SME_I16I64
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
 +
 +HWCAP2_SME_F64F64
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
 +
 +HWCAP2_SME_I8I32
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
 +
 +HWCAP2_SME_F16F32
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
 +
 +HWCAP2_SME_B16F32
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
 +
 +HWCAP2_SME_F32F32
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
 +
 +HWCAP2_SME_FA64
 +
 +    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
 +
+ HWCAP2_WFXT
+ 
+     Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
+ 
  4. Unused AT_HWCAP bits
  -----------------------
  

diff --cc arch/arm64/include/asm/esr.h
Simple merge

diff --cc arch/arm64/include/asm/hwcap.h
index 9f0ce00,909337b..aa443d8
--- 1/arch/arm64/include/asm/hwcap.h
--- 2/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@@ -109,14 -109,7 +109,15 @@@
  #define KERNEL_HWCAP_AFP              __khwcap2_feature(AFP)
  #define KERNEL_HWCAP_RPRES            __khwcap2_feature(RPRES)
  #define KERNEL_HWCAP_MTE3             __khwcap2_feature(MTE3)
 +#define KERNEL_HWCAP_SME              __khwcap2_feature(SME)
 +#define KERNEL_HWCAP_SME_I16I64               __khwcap2_feature(SME_I16I64)
 +#define KERNEL_HWCAP_SME_F64F64               __khwcap2_feature(SME_F64F64)
 +#define KERNEL_HWCAP_SME_I8I32                __khwcap2_feature(SME_I8I32)
 +#define KERNEL_HWCAP_SME_F16F32               __khwcap2_feature(SME_F16F32)
 +#define KERNEL_HWCAP_SME_B16F32               __khwcap2_feature(SME_B16F32)
 +#define KERNEL_HWCAP_SME_F32F32               __khwcap2_feature(SME_F32F32)
 +#define KERNEL_HWCAP_SME_FA64         __khwcap2_feature(SME_FA64)
+ #define KERNEL_HWCAP_WFXT             __khwcap2_feature(WFXT)
  
  /*
   * This yields a mask that user programs can use to figure out what

diff --cc arch/arm64/include/asm/kvm_host.h
index f8f0d30,9e6e870..f24ef94
--- 1/arch/arm64/include/asm/kvm_host.h
--- 2/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@@ -454,7 -441,7 +454,8 @@@ struct kvm_vcpu_arch 
  #define KVM_ARM64_DEBUG_STATE_SAVE_TRBE       (1 << 13) /* Save TRBE context if active  */
  #define KVM_ARM64_FP_FOREIGN_FPSTATE  (1 << 14)
  #define KVM_ARM64_ON_UNSUPPORTED_CPU  (1 << 15) /* Physical CPU not in supported_cpus */
 -#define KVM_ARM64_WFIT                        (1 << 16) /* WFIT instruction trapped */
 +#define KVM_ARM64_HOST_SME_ENABLED    (1 << 16) /* SME enabled for EL0 */
++#define KVM_ARM64_WFIT                        (1 << 17) /* WFIT instruction trapped */
  
  #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
                                 KVM_GUESTDBG_USE_SW_BP | \

diff --cc arch/arm64/include/uapi/asm/hwcap.h
index b0256ce,9dddde1..4bb2cc8
--- 1/arch/arm64/include/uapi/asm/hwcap.h
--- 2/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@@ -79,13 -79,6 +79,14 @@@
  #define HWCAP2_AFP            (1 << 20)
  #define HWCAP2_RPRES          (1 << 21)
  #define HWCAP2_MTE3           (1 << 22)
 -#define HWCAP2_WFXT           (1 << 23)
 +#define HWCAP2_SME            (1 << 23)
 +#define HWCAP2_SME_I16I64     (1 << 24)
 +#define HWCAP2_SME_F64F64     (1 << 25)
 +#define HWCAP2_SME_I8I32      (1 << 26)
 +#define HWCAP2_SME_F16F32     (1 << 27)
 +#define HWCAP2_SME_B16F32     (1 << 28)
 +#define HWCAP2_SME_F32F32     (1 << 29)
 +#define HWCAP2_SME_FA64               (1 << 30)
++#define HWCAP2_WFXT           (1UL << 31)
  
  #endif /* _UAPI__ASM_HWCAP_H */

diff --cc arch/arm64/kernel/cpufeature.c
index 619324b,945190e..78ed5fc
--- 1/arch/arm64/kernel/cpufeature.c
--- 2/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -2491,33 -2443,17 +2492,44 @@@ static const struct arm64_cpu_capabilit
                .matches = has_cpuid_feature,
                .min_field_value = 1,
        },
 +#ifdef CONFIG_ARM64_SME
 +      {
 +              .desc = "Scalable Matrix Extension",
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .capability = ARM64_SME,
 +              .sys_reg = SYS_ID_AA64PFR1_EL1,
 +              .sign = FTR_UNSIGNED,
 +              .field_pos = ID_AA64PFR1_SME_SHIFT,
 +              .field_width = 4,
 +              .min_field_value = ID_AA64PFR1_SME,
 +              .matches = has_cpuid_feature,
 +              .cpu_enable = sme_kernel_enable,
 +      },
 +      /* FA64 should be sorted after the base SME capability */
 +      {
 +              .desc = "FA64",
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .capability = ARM64_SME_FA64,
 +              .sys_reg = SYS_ID_AA64SMFR0_EL1,
 +              .sign = FTR_UNSIGNED,
 +              .field_pos = ID_AA64SMFR0_FA64_SHIFT,
 +              .field_width = 1,
 +              .min_field_value = ID_AA64SMFR0_FA64,
 +              .matches = has_cpuid_feature,
 +              .cpu_enable = fa64_kernel_enable,
 +      },
 +#endif /* CONFIG_ARM64_SME */
+       {
+               .desc = "WFx with timeout",
+               .capability = ARM64_HAS_WFXT,
+               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+               .sys_reg = SYS_ID_AA64ISAR2_EL1,
+               .sign = FTR_UNSIGNED,
+               .field_pos = ID_AA64ISAR2_WFXT_SHIFT,
+               .field_width = 4,
+               .matches = has_cpuid_feature,
+               .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
+       },
        {},
  };
  
@@@ -2651,16 -2587,7 +2663,17 @@@ static const struct arm64_cpu_capabilit
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT),
 +#ifdef CONFIG_ARM64_SME
 +      HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
 +      HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
 +#endif /* CONFIG_ARM64_SME */
        {},
  };
  

diff --cc arch/arm64/kernel/cpuinfo.c
index 8a8136a,781eab3..8eff0a3
--- 1/arch/arm64/kernel/cpuinfo.c
--- 2/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@@ -98,14 -98,7 +98,15 @@@ static const char *const hwcap_str[] = 
        [KERNEL_HWCAP_AFP]              = "afp",
        [KERNEL_HWCAP_RPRES]            = "rpres",
        [KERNEL_HWCAP_MTE3]             = "mte3",
 +      [KERNEL_HWCAP_SME]              = "sme",
 +      [KERNEL_HWCAP_SME_I16I64]       = "smei16i64",
 +      [KERNEL_HWCAP_SME_F64F64]       = "smef64f64",
 +      [KERNEL_HWCAP_SME_I8I32]        = "smei8i32",
 +      [KERNEL_HWCAP_SME_F16F32]       = "smef16f32",
 +      [KERNEL_HWCAP_SME_B16F32]       = "smeb16f32",
 +      [KERNEL_HWCAP_SME_F32F32]       = "smef32f32",
 +      [KERNEL_HWCAP_SME_FA64]         = "smefa64",
+       [KERNEL_HWCAP_WFXT]             = "wfxt",
  };
  
  #ifdef CONFIG_COMPAT

diff --cc arch/arm64/kvm/sys_regs.c
Simple merge

diff --cc arch/arm64/tools/cpucaps
Simple merge