module_param(ignore_443_358, int, 0644);
MODULE_PARM_DESC(ignore_443_358, "ignore_443_358\n");
+unsigned int cvd_reg87_pal;
+static unsigned int acd_vde_config = 0x00170107;
+
static unsigned int acd_h_config = 0x8e035e;
module_param(acd_h_config, uint, 0664);
MODULE_PARM_DESC(acd_h_config, "acd_h_config");
}
}
+ cvd_reg87_pal = R_APB_REG(CVD2_REG_87);
+ acd_vde_config = R_APB_REG(ACD_REG_2E);
+
/* enable CVD2 */
W_APB_BIT(CVD2_RESET_REGISTER, 0, SOFT_RST_BIT, SOFT_RST_WID);
}
return;
}
/*write default de to register*/
- W_APB_REG(ACD_REG_2E, (rf_acd_table[cvd2->config_fmt-
- TVIN_SIG_FMT_CVBS_NTSC_M][0x2e]));
+ W_APB_REG(ACD_REG_2E, acd_vde_config);
if (tvafe_dbg_print & TVAFE_DBG_SMR)
tvafe_pr_info("%s set default de %s.\n",
__func__, tvin_sig_fmt_str(cvd2->config_fmt));
#endif
/*pali to nosignal,restore default vstart-end after auto de*/
if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_PAL_I) {
- W_APB_REG(ACD_REG_2E, 0x170137);
+ W_APB_REG(ACD_REG_2E, acd_vde_config);
if (tvafe_dbg_print & TVAFE_DBG_SMR)
pr_info("[tvafe..] %s: reset auto de.\n", __func__);
}
W_APB_REG(CVD2_YC_SEPARATION_CONTROL, 0x12);
if (R_APB_REG(CVD2_H_LOOP_MAXSTATE) != 0xd)
W_APB_REG(CVD2_H_LOOP_MAXSTATE, 0xd);
- if (R_APB_REG(CVD2_REG_87) != 0x0)
- W_APB_REG(CVD2_REG_87, 0x0);
+ if (R_APB_REG(CVD2_REG_87) != cvd_reg87_pal)
+ W_APB_REG(CVD2_REG_87, cvd_reg87_pal);
W_APB_REG(ACD_REG_2D, acd_h_back);
W_APB_BIT(CVD2_ACTIVE_VIDEO_HSTART, cvd_2e,
HACTIVE_START_BIT, HACTIVE_START_WID);
W_APB_REG(CVD2_YC_SEPARATION_CONTROL, 0x12);
if (R_APB_REG(CVD2_H_LOOP_MAXSTATE) != 0xd)
W_APB_REG(CVD2_H_LOOP_MAXSTATE, 0xd);
- if (R_APB_REG(CVD2_REG_87) != 0x0)
- W_APB_REG(CVD2_REG_87, 0x0);
+ if (R_APB_REG(CVD2_REG_87) != cvd_reg87_pal)
+ W_APB_REG(CVD2_REG_87, cvd_reg87_pal);
W_APB_REG(ACD_REG_2D, acd_h_back);
W_APB_BIT(CVD2_ACTIVE_VIDEO_HSTART, cvd_2e,
{CVD2_3DCOMB_FILTER, 0x0f, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
- /* fix Purple and green junctions is wider */
- {CVD2_REG_FA, 0x00, 0x80},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
static struct tvafe_reg_table_s cvbs_ntsc443_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
/*chroma state adjust dynamicly*/
{CVD2_CHROMA_LOOPFILTER_STATE, 0x0a, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
{ACD_REG_89, 0x80010004, 0xffffffff},
{ACD_REG_8A, 0x100004, 0xffffffff},
{ACD_REG_8C, 0x38000, 0xffffffff},
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*for moonoscope pattern color flash*/
{ACD_REG_22, 0x2020000, 0xffffffff},
{CVD2_NOISE_THRESHOLD, 0xff, 0xff},
static struct tvafe_reg_table_s cvbs_pal60_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
static struct tvafe_reg_table_s cvbs_palcn_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
static struct tvafe_reg_table_s cvbs_ntsc50_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
{0xffffffff, 0, 0},
};
{ACD_REG_22, 0x2020000, 0xffffffff},
{CVD2_NOISE_THRESHOLD, 0xff, 0xff},
{CVD2_NON_STANDARD_SIGNAL_THRESHOLD, 0x20, 0xff},
+ {CVD2_REG_87, 0xc0, 0xc0},
+ {CVD2_REG_FA, 0x00, 0xa0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
+ {CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};