Add more test descriptions based on exiting comments.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
* this checks whether they actually work.
*/
+IGT_TEST_DESCRIPTION("Check whether the libdrm vma limiter works.");
+
/* we do both cpu and gtt maps, so only need half of 64k to exhaust */
#define BO_ARRAY_SIZE 35000
drm_intel_bo *bos[BO_ARRAY_SIZE];
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Test minimal bo_create and batchbuffer exec.");
+
/*
- * Testcase: Minmal bo_create and batchbuffer exec
+ * Testcase: Minimal bo_create and batchbuffer exec
*
* Originally this caught an kernel oops due to the unchecked assumption that
* objects have size > 0.
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations"
+ " for STATE_BASE_ADDRESS command packets.");
+
#define USE_LUT (1 << 12)
/* Simulates SNA behaviour using negative self-relocations for
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial"
+ " cachelines.");
+
/*
* Testcase: snoop consistency when touching partial cachelines
*
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test of pread/pwrite behavior when writing to active"
+ " buffers.");
+
int fd, devid, gen;
struct intel_batchbuffer *batch;
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test the relocations through the CPU domain.");
+
static uint32_t use_blt;
static void copy(int fd, uint32_t batch, uint32_t src, uint32_t dst)
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test the CS prefetch behaviour on batches.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Check whether we correctly invalidate the cs tlb.");
+
#define LOCAL_I915_EXEC_VEBOX (4<<0)
#define BATCH_SIZE (1024*1024)
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Negative test cases for destroy contexts.");
+
struct local_drm_i915_context_destroy {
__u32 ctx_id;
__u32 pad;
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Test that context cannot be submitted to unsupported"
+ " rings.");
+
/* Copied from gem_exec_nop.c */
static int exec(int fd, uint32_t handle, int ring, int ctx_id)
{
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic test for memory and refcount leaks.");
+
/* options */
int num_contexts = 10;
int uncontexted = 0; /* test only context create/destroy */
#include "igt_aux.h"
#include "igt_debugfs.h"
+IGT_TEST_DESCRIPTION("Test basic context switch functionality.");
+
struct local_drm_i915_gem_context_destroy {
__u32 ctx_id;
__u32 pad;
* on the second batch. This hopefully catches races in our irq acknowledgement.
*/
+IGT_TEST_DESCRIPTION("Basic check for missed IRQs on blt ring.");
+
#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
#define MI_DO_COMPARE (1<<21)
* at hitting the missed irq bug that's worked around with the HWSTAM irq write.
*/
+IGT_TEST_DESCRIPTION("Check ring<->cpu sync using a dummy reloc.");
#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
#define MI_DO_COMPARE (1<<21)
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Run a couple of big batches to force the unbind on"
+ " misalignment code.");
+
#define HEIGHT 256
#define WIDTH 1024
#include "eviction_common.c"
+IGT_TEST_DESCRIPTION("Run a couple of big batches to force the eviction"
+ " code.");
+
#define HEIGHT 256
#define WIDTH 1024
* If it does not, it'll oops somewhen later on because we don't expect that.
*/
+IGT_TEST_DESCRIPTION("Test whether the kernel rejects relocations with non-gpu"
+ " domains.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Run a large nop batch to stress test the error capture"
+ " code.");
+
#define BATCH_SIZE (1024*1024)
static void exec(int fd, uint32_t handle, uint32_t reloc_ofs)
* To be really evil, use a gtt mmap for them.
*/
+IGT_TEST_DESCRIPTION("Submit patches with relocations in memory that will"
+ " fault.");
+
#define OBJECT_SIZE 16384
#define COPY_BLT_CMD_NOLEN (2<<29|0x53<<22)
*
*/
-/* Exercises the basic execbuffer using theh andle LUT interface */
+/* Exercises the basic execbuffer using the handle LUT interface */
#include <stdlib.h>
#include <stdio.h>
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT"
+ " interface.");
+
#define BATCH_SIZE (1024*1024)
#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
+
#define WIDTH 1024
#define HEIGHT 1024
#define OBJECT_SIZE (4*WIDTH*HEIGHT)
#include "intel_bufmgr.h"
#include "igt_debugfs.h"
+IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close races.");
+
/* Testcase: check for flink/open vs. gem close races
*
* The gem flink open ioctl had a little race with gem close which could result
#include "drmtest.h"
#include "intel_io.h"
+IGT_TEST_DESCRIPTION("Check whether gtt tlbs for cpu access are correctly"
+ " invalidated.");
+
#define OBJ_SIZE (1024*1024)
#define PAGE_SIZE 4096
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Provoke the hangcheck timer on an otherwise idle"
+ " system.");
+
/*
* Testcase: Provoke the hangcheck timer on an otherwise idle system
*
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test doing many blits with a working set larger than the"
+ " aperture size.");
+
#define WIDTH 512
#define HEIGHT 512
*
*/
-/* Exercises the basic execbuffer using theh andle LUT interface */
+/* Exercises the basic execbuffer using the handle LUT interface */
#include <stdlib.h>
#include <stdio.h>
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT"
+ " interface.");
+
#define BATCH_SIZE (1024*1024)
#define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Checks that the kernel reports EFAULT when trying to use"
+ " purged bo.");
+
#define OBJECT_SIZE (1024*1024)
/* Testcase: checks that the kernel reports EFAULT when trying to use purged bo
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic test for the media_fill() function, a very simple"
+ " workload for the Media pipeline.");
+
#define WIDTH 64
#define STRIDE (WIDTH)
#define HEIGHT 64
#include "ioctl_wrappers.h"
#include "drmtest.h"
+IGT_TEST_DESCRIPTION("Checks whether the kernel handles mmap offset exhaustion"
+ " correctly.");
+
#define OBJECT_SIZE (1024*1024)
/* Testcase: checks whether the kernel handles mmap offset exhaustion correctly
#include "i830_reg.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic check of ring<->ring sync using a dummy reloc.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#include "intel_io.h"
#include "i830_reg.h"
+IGT_TEST_DESCRIPTION("Basic check of non-secure batches.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
+ " cachelines.");
+
/*
* Testcase: pwrite/pread consistency when touching partial cachelines
*
#include "igt_debugfs.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test persistent relocations as used by uxa/libva.");
+
/*
* Testcase: Persistent relocations as used by uxa/libva
*
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Exercises pinning of small buffer objects.");
+
#define COPY_BLT_CMD (2<<29|0x53<<22|0x6)
#define BLT_WRITE_ALPHA (1<<21)
#define BLT_WRITE_RGB (1<<20)
#include "intel_chipset.h"
#include "intel_io.h"
+IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t devid;
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of"
+ " just-drawn-to buffers.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static const int width = 512, height = 512;
#include "drmtest.h"
#include "intel_io.h"
+IGT_TEST_DESCRIPTION("Check that kernel relocation overflows are caught.");
+
/*
* Testcase: Kernel relocation overflows are caught.
*/
#include "igt_debugfs.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test kernel relocations vs. gpu races.");
+
/*
* Testcase: Kernel relocations vs. gpu races
*
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Basic test for the render_copy() function.");
+
#define WIDTH 512
#define STRIDE (WIDTH*4)
#define HEIGHT 512
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Advanced test for the render_copy() function.");
+
#define WIDTH 512
#define STRIDE (WIDTH*4)
#define HEIGHT 512
#include "intel_batchbuffer.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Ensure inter-ring dependencies are respected.");
+
#define WIDTH 512
#define HEIGHT 512
#define NUM_BUSY_BUFFERS 32
#include "i830_reg.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic check of ring<->ring sync using a dummy reloc.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Runs blitcopy -> rendercopy with multiple buffers over"
+ " wrap boundary.");
+
static int devid;
static int card_index = 0;
static uint32_t last_seqno = 0;
#include "intel_chipset.h"
#include "intel_io.h"
+IGT_TEST_DESCRIPTION("Check for proper synchronization of tiling changes vs."
+ " tiled gpu access.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t devid;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Check set_tiling vs gtt mmap coherency.");
+
#define OBJECT_SIZE (1024*1024)
#define TEST_STRIDE (1024*4)
#include "drmtest.h"
#include "intel_io.h"
+IGT_TEST_DESCRIPTION("Check set_tiling vs pwrite coherency.");
+
#define OBJECT_SIZE (1024*1024)
#define TEST_STRIDE (1024*4)
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic blitter MI check using MI_STORE_DATA_IMM.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic bsd MI check using MI_STORE_DATA_IMM.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic render MI check using MI_STORE_DATA_IMM.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Basic vebox MI check using MI_STORE_DATA_IMM.");
+
#define LOCAL_I915_EXEC_VEBOX (4<<0)
static drm_intel_bufmgr *bufmgr;
#include "intel_chipset.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("General gem coherency test.");
+
#define CMD_POLY_STIPPLE_OFFSET 0x7906
#define DUCTAPE 0xdead0001
#include "ioctl_wrappers.h"
#include "intel_bufmgr.h"
+IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
+
/* Testcase: check parallel access to tiled memory
*
* Parallel access to tiled memory caused sigbus
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger"
+ " than the aperture size.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static int width = 512, height = 512;
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
+ " cachelines.");
+
/*
* Testcase: pwrite/pread consistency when touching partial cachelines
*
#include "intel_io.h"
#include "intel_chipset.h"
+
+IGT_TEST_DESCRIPTION("Test pread behavior on tiled objects with respect to the"
+ " reported swizzling value.");
+
#define WIDTH 512
#define HEIGHT 512
static uint32_t linear[WIDTH * HEIGHT];
*/
/*
- * Testcase: Test swizzling by testing pwrite does the invers of pread
+ * Testcase: Test swizzling by testing pwrite does the inverse of pread
*
* Together with the explicit pread testcase, this should cover our swizzle
* handling.
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Test swizzling by testing pwrite does the inverse of"
+ " pread.");
+
#define WIDTH 512
#define HEIGHT 512
static uint32_t linear[WIDTH * HEIGHT];
#include "intel_io.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Exercise swizzle code for swapping.");
+
#define WIDTH 512
#define HEIGHT 512
#define LINEAR_DWORDS (4 * WIDTH * HEIGHT)
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("This is a test of write-combining mmap's behavior on"
+ " tiled objects with respect to the reported swizzling"
+ " value.");
+
#define WIDTH 512
#define HEIGHT 512
#define SIZE (WIDTH*HEIGHT*sizeof(uint32_t))
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Check that max fence stride works.");
+
static void do_test_invalid_tiling(int fd, uint32_t handle, int tiling, int stride)
{
igt_assert(__gem_set_tiling(fd, handle, tiling, tiling ? stride : 0) == -EINVAL);
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t devid;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Test unreferencing of active buffers.");
+
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *load_bo;
#include "i830_reg.h"
#include "igt_aux.h"
+IGT_TEST_DESCRIPTION("Check read/write syncpoints when switching rings.");
+
#define LOCAL_I915_EXEC_VEBOX (4<<0)
static drm_intel_bufmgr *bufmgr;
#include "intel_io.h"
#include "intel_chipset.h"
+IGT_TEST_DESCRIPTION("Exercise a suspect workaround required for"
+ " FORCEWAKE_MT.");
+
#define FORCEWAKE_MT 0xa188
struct thread {
#include "igt_kms.h"
#include "ioctl_wrappers.h"
+IGT_TEST_DESCRIPTION("Test that a page flip from a tiled buffer to a linear"
+ " one works correctly.");
+
typedef struct {
int drm_fd;
igt_display_t display;
#include "drmtest.h"
#include "igt_edid.h"
+IGT_TEST_DESCRIPTION("Check the debugfs force connector/edid features work"
+ " correctly.");
+
int
main (int argc, char **argv)
{
#include "drmtest.h"
#include "igt_debugfs.h"
+IGT_TEST_DESCRIPTION("Check whether prime import/export works on the same"
+ " device.");
+
#define BO_SIZE (16*1024)
static char counter;