riscv: thead: Add support for the XTheadMac ISA extension

The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh

To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4

Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gcc/ChangeLog:

	* config/riscv/riscv.md (maddhisi4): New expand.
	(msubhisi4): New expand.
	* config/riscv/thead.md (*th_mula<mode>): New pattern.
	(*th_mulawsi): New pattern.
	(*th_mulawsi2): New pattern.
	(*th_maddhisi4): New pattern.
	(*th_sextw_maddhisi4): New pattern.
	(*th_muls<mode>): New pattern.
	(*th_mulswsi): New pattern.
	(*th_mulswsi2): New pattern.
	(*th_msubhisi4): New pattern.
	(*th_sextw_msubhisi4): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadmac-mula-muls.c: New test.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 34d4a20..1a9c3e0 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3115,6 +3115,24 @@
     FAIL;
 })
 
+(define_expand "maddhisi4"
+  [(set (match_operand:SI 0 "register_operand")
+       (plus:SI
+         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"))
+                  (sign_extend:SI (match_operand:HI 2 "register_operand")))
+         (match_operand:SI 3 "register_operand")))]
+  "TARGET_XTHEADMAC"
+)
+
+(define_expand "msubhisi4"
+  [(set (match_operand:SI 0 "register_operand")
+       (minus:SI
+         (match_operand:SI 3 "register_operand")
+         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"))
+                  (sign_extend:SI (match_operand:HI 2 "register_operand")))))]
+  "TARGET_XTHEADMAC"
+)
+
 (include "bitmanip.md")
 (include "crypto.md")
 (include "sync.md")

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 88b6a95..ce709ca 100644 (file)
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -138,3 +138,124 @@
    th.mveqz\t%0,%z3,%1"
   [(set_attr "type" "condmove")
    (set_attr "mode" "<GPR:MODE>")])
+
+;; XTheadMac
+
+(define_insn "*th_mula<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+             (plus:X (mult:X (match_operand:X 1 "register_operand" "r")
+                             (match_operand:X 2 "register_operand" "r"))
+                     (match_operand:X 3 "register_operand" "0")))]
+  "TARGET_XTHEADMAC"
+  "th.mula\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "<MODE>")]
+)
+
+(define_insn "*th_mulawsi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (sign_extend:DI
+         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+                           (match_operand:SI 2 "register_operand" "r"))
+                  (match_operand:SI 3 "register_operand" "0"))))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulaw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_mulawsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+             (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+                               (match_operand:SI 2 "register_operand" "r"))
+                      (match_operand:SI 3 "register_operand" "0")))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulaw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_maddhisi4"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+         (plus:SI
+           (mult:SI
+             (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+             (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))
+           (match_operand:SI 3 "register_operand" " 0")))]
+  "TARGET_XTHEADMAC"
+  "th.mulah\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_sextw_maddhisi4"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (sign_extend:DI
+         (plus:SI
+           (mult:SI
+             (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+             (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))
+           (match_operand:SI 3 "register_operand" " 0"))))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulah\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_muls<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+             (minus:X (match_operand:X 3 "register_operand" "0")
+                      (mult:X (match_operand:X 1 "register_operand" "r")
+                              (match_operand:X 2 "register_operand" "r"))))]
+  "TARGET_XTHEADMAC"
+  "th.muls\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "<MODE>")]
+)
+
+(define_insn "*th_mulswsi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (sign_extend:DI
+         (minus:SI (match_operand:SI 3 "register_operand" "0")
+                   (mult:SI (match_operand:SI 1 "register_operand" "r")
+                            (match_operand:SI 2 "register_operand" "r")))))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulsw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_mulswsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (minus:SI (match_operand:SI 3 "register_operand" "0")
+                 (mult:SI (match_operand:SI 1 "register_operand" "r")
+                          (match_operand:SI 2 "register_operand" "r"))))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulsw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_msubhisi4"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (minus:SI (match_operand:SI 3 "register_operand" " 0")
+         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+           (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))))]
+  "TARGET_XTHEADMAC"
+  "th.mulsh\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_sextw_msubhisi4"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (sign_extend:DI
+         (minus:SI (match_operand:SI 3 "register_operand" " 0")
+           (mult:SI
+             (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+             (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))))))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulsh\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c b/gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c
new file mode 100644 (file)
index 0000000..751a4be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadmac" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadmac" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
+
+long f_mula(long a, long b, long c)
+{
+  return a + b * c;
+}
+
+long f_muls(long a, long b, long c)
+{
+  return a - b * c;
+}
+
+#if __riscv_xlen == 64
+int f_mulaw(int a, int b, int c)
+{
+  return a + b * c;
+}
+
+int f_mulsw(int a, int b, int c)
+{
+  return a - b * c;
+}
+#endif
+
+long f_mulah(int a, unsigned short b, unsigned short c)
+{
+  return a + (int)(short)b * (int)(short)c;
+}
+
+long f_mulsh(int a, unsigned short b, unsigned short c)
+{
+  return a - (int)(short)b * (int)(short)c;
+}
+
+/* { dg-final { scan-assembler-times "th.mula\t" 1 } } */
+/* { dg-final { scan-assembler-times "th.muls\t" 1 } } */
+/* { dg-final { scan-assembler-times "th.mulaw\t" 1 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "th.mulsw\t" 1 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */
+/* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */