clk: tegra: add TEGRA_PERIPH_NO_GATE

Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b5feccc..d62b396 100644 (file)
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -170,6 +170,14 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
        .disable = clk_periph_disable,
 };
 
+const struct clk_ops tegra_clk_periph_no_gate_ops = {
+       .get_parent = clk_periph_get_parent,
+       .set_parent = clk_periph_set_parent,
+       .recalc_rate = clk_periph_recalc_rate,
+       .round_rate = clk_periph_round_rate,
+       .set_rate = clk_periph_set_rate,
+};
+
 static struct clk *_tegra_clk_register_periph(const char *name,
                        const char **parent_names, int num_parents,
                        struct tegra_clk_periph *periph,
@@ -181,11 +189,15 @@ static struct clk *_tegra_clk_register_periph(const char *name,
        struct tegra_clk_periph_regs *bank;
        bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
 
-       flags |= periph->gate.flags & TEGRA_PERIPH_NO_DIV ?
-                       CLK_SET_RATE_PARENT : 0;
+       if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
+               flags |= CLK_SET_RATE_PARENT;
+               init.ops = &tegra_clk_periph_nodiv_ops;
+       } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
+               init.ops = &tegra_clk_periph_no_gate_ops;
+       else
+               init.ops = &tegra_clk_periph_ops;
 
        init.name = name;
-       init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
        init.flags = flags;
        init.parent_names = parent_names;
        init.num_parents = num_parents;

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index e8d6f2f..958d4f4 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -135,6 +135,12 @@
                        _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
                        NULL)
 
+#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)     \
+       TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,     \
+                             29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
+                             0, TEGRA_PERIPH_NO_GATE, _clk_id,\
+                             _parents##_idx, 0, _lock)
+
 #define INT(_name, _parents, _offset,  \
                            _clk_num, _gate_flags, _clk_id)     \
        TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index f984ebe..40fb011 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -391,6 +391,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_ON_APB BIT(2)
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 #define TEGRA_PERIPH_NO_DIV BIT(4)
+#define TEGRA_PERIPH_NO_GATE BIT(5)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;