drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()
authorAshutosh Dixit <ashutosh.dixit@intel.com>
Mon, 14 Mar 2022 16:13:10 +0000 (09:13 -0700)
committerAnshuman Gupta <anshuman.gupta@intel.com>
Wed, 6 Apr 2022 10:17:38 +0000 (15:47 +0530)
Because VLV_GT_RENDER_RC6 == GEN6_GT_GFX_RC6, the IS_VALLEYVIEW() check is
not needed. Neither is the check present in other code paths which call
intel_rc6_residency_ns() (in functions gen6_drpc(), rc6_residency() and
rc6_residency_ms_show()).

v2: Elimintate VLV_GT_RENDER_RC6 #define (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220314161310.6468-1-ashutosh.dixit@intel.com
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/i915_pmu.c

index 4a1c74b..437e96b 100644 (file)
@@ -113,7 +113,7 @@ static int vlv_drpc(struct seq_file *m)
        seq_printf(m, "Media Power Well: %s\n",
                   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
 
-       print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
+       print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
        print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
 
        return fw_domains_show(m, NULL);
index 18d158d..1545867 100644 (file)
 #define   VLV_MEDIA_RC6_COUNT_EN               (1 << 1)
 #define   VLV_RENDER_RC6_COUNT_EN              (1 << 0)
 #define GEN6_GT_GFX_RC6                                _MMIO(0x138108)
-#define VLV_GT_RENDER_RC6                      _MMIO(0x138108)
 #define VLV_GT_MEDIA_RC6                       _MMIO(0x13810c)
 
 #define GEN6_GT_GFX_RC6p                       _MMIO(0x13810c)
index cfc2104..3e3b095 100644 (file)
@@ -148,10 +148,7 @@ static u64 __get_rc6(struct intel_gt *gt)
        struct drm_i915_private *i915 = gt->i915;
        u64 val;
 
-       val = intel_rc6_residency_ns(&gt->rc6,
-                                    IS_VALLEYVIEW(i915) ?
-                                    VLV_GT_RENDER_RC6 :
-                                    GEN6_GT_GFX_RC6);
+       val = intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6);
 
        if (HAS_RC6p(i915))
                val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6p);