Improve documentation of register constraints.

While looking at PR target/64532- I realized we haven't documented all
the register constraints. I'm not documenting the other immediate
constraints as it is not clear to me how much of that is actually
useful yet and I don't have the time this afternoon to clean this up.

Built documentation and looked at it.

Applied.

Ramana

From-SVN: r219847

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4e03d90..8a5a1de 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-19  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       PR target/64532
+       * doc/md.texi (ARM Options): Document register constraints.
+
 2015-01-19  Jiong Wang  <jiong.wang@arm.com>
            Andrew Pinski  <apinski@cavium.com>
 

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 7bc7842..0050ba7 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1800,8 +1800,30 @@ Any const_double value.
 
 @item ARM family---@file{config/arm/constraints.md}
 @table @code
+
+@item h
+In Thumb state, the core registers @code{r8}-@code{r15}.
+
+@item k
+The stack pointer register.
+
+@item l
+In Thumb State the core registers @code{r0}-@code{r7}.  In ARM state this
+is an alias for the @code{r} constraint.
+
+@item t
+VFP floating-point registers @code{s0}-@code{s31}.  Used for 32 bit values.
+
 @item w
-VFP floating-point register
+VFP floating-point registers @code{d0}-@code{d31} and the appropriate
+subset @code{d0}-@code{d15} based on command line options.
+Used for 64 bit values only.  Not valid for Thumb1.
+
+@item y
+The iWMMX co-processor registers.
+
+@item z
+The iWMMX GR registers.
 
 @item G
 The floating-point constant 0.0