x86/fpu: Mask out the invalid MXCSR bits properly
authorBorislav Petkov <bp@suse.de>
Fri, 15 Oct 2021 10:46:25 +0000 (12:46 +0200)
committerBorislav Petkov <bp@suse.de>
Sat, 16 Oct 2021 10:37:50 +0000 (12:37 +0200)
This is a fix for the fix (yeah, /facepalm).

The correct mask to use is not the negation of the MXCSR_MASK but the
actual mask which contains the supported bits in the MXCSR register.

Reported and debugged by Ville Syrjälä <ville.syrjala@linux.intel.com>

Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ser Olmy <ser.olmy@protonmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@intel.com
arch/x86/kernel/fpu/signal.c

index fa17a27390ab0128a136592a2cc4dbde6ac93708..831b25c5e70581aeb490e951a7bb8842a5dbc0be 100644 (file)
@@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx,
                                return -EINVAL;
                } else {
                        /* Mask invalid bits out for historical reasons (broken hardware). */
-                       fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
+                       fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
                }
 
                /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */