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arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider
author
Sibi Sankar
<sibis@codeaurora.org>
Thu, 27 Feb 2020 10:56:31 +0000
(16:26 +0530)
committer
Bjorn Andersson
<bjorn.andersson@linaro.org>
Fri, 6 Mar 2020 05:47:05 +0000
(21:47 -0800)
Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link:
https://lore.kernel.org/r/20200227105632.15041-8-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm64/boot/dts/qcom/sc7180.dtsi
patch
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diff --git
a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 9592213652662e3611cde93c2629398f4d805619..c51fda655195a5f186861187ad193b23757e0b5e 100644
(file)
--- a/
arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/
arch/arm64/boot/dts/qcom/sc7180.dtsi
@@
-1988,6
+1988,16
@@
};
};
+ osm_l3: interconnect@18321000 {
+ compatible = "qcom,sc7180-osm-l3";
+ reg = <0 0x18321000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;