OneNAND: Define OneNAND controller registers

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/include/s5pc1xx-onenand.h b/include/s5pc1xx-onenand.h
index a7c24f7..e16a954 100644 (file)
--- a/include/s5pc1xx-onenand.h
+++ b/include/s5pc1xx-onenand.h
@@ -15,6 +15,7 @@
 #define INT_ERR_MASK_OFFSET    0x0040
 #define INT_ERR_ACK_OFFSET     0x0050
 #define ECC_ERR_STAT_OFFSET    0x0060
+#define ECC_ERR_STAT_1_OFFSET  0x0060
 #define MANUFACT_ID_OFFSET     0x0070
 #define DEVICE_ID_OFFSET       0x0080
 #define DATA_BUF_SIZE_OFFSET   0x0090
@@ -24,13 +25,24 @@
 #define FBA_WIDTH_OFFSET       0x00D0
 #define FPA_WIDTH_OFFSET       0x00E0
 #define FSA_WIDTH_OFFSET       0x00F0
+#define SYNC_MODE_OFFSET       0x0130
 #define TRANS_SPARE_OFFSET     0x0140
+#define ERR_PAGE_ADDR_OFFSET   0x0180
 #define INT_PIN_ENABLE_OFFSET  0x01A0
 #define ACC_CLOCK_OFFSET       0x01C0
+#define ERR_BLK_ADDR_OFFSET    0x01E0
 #define FLASH_VER_ID_OFFSET    0x01F0
 #define WATCHDOG_CNT_LOW_OFFSET        0x0260
 #define WATCHDOG_CNT_HI_OFFSET 0x0270
 #define COLD_RESET_DELAY_OFFSET        0x02A0
+#define DDP_DEVICE_OFFSET      0x02B0
+#define MULTI_PLANE_OFFSET     0x02C0
+#define TRANS_MODE_OFFSET      0x02E0
+#define ECC_ERR_STAT_2_OFFSET  0x0300
+#define ECC_ERR_STAT_3_OFFSET  0x0310
+#define ECC_ERR_STAT_4_OFFSET  0x0320
+#define DEV_PAGE_SIZE_OFFSET   0x0340
+#define INT_MON_STATUS_OFFSET  0x0390
 
 #define MEM_CFG0_REG           __REG(S5P_ONENAND_BASE + MEM_CFG_OFFSET)
 #define BURST_LEN0_REG         __REG(S5P_ONENAND_BASE + BURST_LEN_OFFSET)
@@ -39,20 +51,33 @@
 #define INT_ERR_MASK0_REG      __REG(S5P_ONENAND_BASE + INT_ERR_MASK_OFFSET)
 #define INT_ERR_ACK0_REG       __REG(S5P_ONENAND_BASE + INT_ERR_ACK_OFFSET)
 #define ECC_ERR_STAT0_REG      __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_OFFSET)
+#define ECC_ERR_STAT_1_REG     __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_1_OFFSET)
 #define MANUFACT_ID0_REG       __REG(S5P_ONENAND_BASE + MANUFACT_ID_OFFSET)
 #define DEVICE_ID0_REG         __REG(S5P_ONENAND_BASE + DEVICE_ID_OFFSET)
 #define DATA_BUF_SIZE0_REG     __REG(S5P_ONENAND_BASE + DATA_BUF_SIZE_OFFSET)
+#define BOOT_BUF_SIZE0_REG     __REG(S5P_ONENAND_BASE + BOOT_BUF_SIZE_OFFSET)
 #define FBA_WIDTH0_REG         __REG(S5P_ONENAND_BASE + FBA_WIDTH_OFFSET)
 #define FPA_WIDTH0_REG         __REG(S5P_ONENAND_BASE + FPA_WIDTH_OFFSET)
 #define FSA_WIDTH0_REG         __REG(S5P_ONENAND_BASE + FSA_WIDTH_OFFSET)
+#define SYNC_MODE_REG          __REG(S5P_ONENAND_BASE + SYNC_MODE_OFFSET)
 #define TRANS_SPARE0_REG       __REG(S5P_ONENAND_BASE + TRANS_SPARE_OFFSET)
+#define ERR_PAGE_ADDR_REG      __REG(S5P_ONENAND_BASE + ERR_PAGE_ADDR_OFFSET)
 #define DBS_DFS_WIDTH0_REG     __REG(S5P_ONENAND_BASE + DBS_DFS_WIDTH_OFFSET)
 #define INT_PIN_ENABLE0_REG    __REG(S5P_ONENAND_BASE + INT_PIN_ENABLE_OFFSET)
 #define ACC_CLOCK0_REG         __REG(S5P_ONENAND_BASE + ACC_CLOCK_OFFSET)
+#define ERR_BLK_ADDR_REG       __REG(S5P_ONENAND_BASE + ERR_BLK_ADDR_OFFSET)
 #define FLASH_VER_ID0_REG      __REG(S5P_ONENAND_BASE + FLASH_VER_ID_OFFSET)
 #define WATCHDOG_CNT_LOW_REG   __REG(S5P_ONENAND_BASE + WATCHDOG_CNT_LOW_OFFSET)
 #define WATCHDOG_CNT_HI_REG    __REG(S5P_ONENAND_BASE + WATCHDOG_CNT_HI_OFFSET)
 #define COLD_RESET_DELAY_REG   __REG(S5P_ONENAND_BASE + COLD_RESET_DELAY_OFFSET)
+#define TRANS_MODE_REG         __REG(S5P_ONENAND_BASE + TRANS_MODE_OFFSET)
+#define DDP_DEVICE_REG         __REG(S5P_ONENAND_BASE + DDP_DEVICE_OFFSET)
+#define MULTI_PLANE_REG                __REG(S5P_ONENAND_BASE + MULTI_PLANE_OFFSET)
+#define ECC_ERR_STAT_2_REG     __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_2_OFFSET)
+#define ECC_ERR_STAT_3_REG     __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_3_OFFSET)
+#define ECC_ERR_STAT_4_REG     __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_4_OFFSET)
+#define DEV_PAGE_SIZE_REG      __REG(S5P_ONENAND_BASE + DEV_PAGE_SIZE_OFFSET)
+#define INT_MON_STATUS_REG     __REG(S5P_ONENAND_BASE + INT_MON_STATUS_OFFSET)
 
 #define ONENAND_MEM_RESET_HOT  0x3
 #define ONENAND_MEM_RESET_COLD 0x2