devid == PCI_CHIP_E7221_G || \
devid == PCI_CHIP_I915_GM)
+#define IS_945GM(devid) (devid == PCI_CHIP_I945_GM || \
+ devid == PCI_CHIP_I945_GME)
+
#define IS_945(devid) (devid == PCI_CHIP_I945_G || \
devid == PCI_CHIP_I945_GM || \
devid == PCI_CHIP_I945_GME || \
# define I830_PRIMARY_RING_1_DONE (1 << 1)
# define I830_PRIMARY_RING_0_DONE (1 << 0)
+#define NOPID 0x2094
+
#define SCPD0 0x209c /* debug */
#define INST_PS 0x20c4
#define IPEIR_I965 0x2064 /* i965 */
DEFINEREG(PCH_PP_DIVISOR),
};
+static struct reg_debug i945gm_mi_regs[] = {
+ DEFINEREG(PGETBL_CTL),
+ DEFINEREG(PGTBL_ER),
+ DEFINEREG(EXCC),
+ DEFINEREG(HWS_PGA),
+ DEFINEREG(IPEIR),
+ DEFINEREG(IPEHR),
+ DEFINEREG(INST_DONE),
+ DEFINEREG(NOPID),
+ DEFINEREG(HWSTAM),
+ DEFINEREG(SCPD0),
+ DEFINEREG(IER),
+ DEFINEREG(IIR),
+ DEFINEREG(IMR),
+ DEFINEREG(ISR),
+ DEFINEREG(EIR),
+ DEFINEREG(EMR),
+ DEFINEREG(ESR),
+ DEFINEREG(INST_PM),
+ DEFINEREG(ECOSKPD),
+};
+
+static void
+i945_dump_mi_regs(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(i945gm_mi_regs); i++) {
+ uint32_t val = INREG(i945gm_mi_regs[i].reg);
+
+ if (i945gm_mi_regs[i].debug_output != NULL) {
+ char *debug = NULL;
+ i945gm_mi_regs[i].debug_output(&debug,
+ i945gm_mi_regs
+ [i].reg,
+ val);
+ if (debug != NULL) {
+ printf("%30.30s: 0x%08x (%s)\n",
+ i945gm_mi_regs[i].name,
+ (unsigned int)val, debug);
+ free(debug);
+ }
+ } else {
+ printf("%30.30s: 0x%08x\n", i945gm_mi_regs[i].name,
+ (unsigned int)val);
+ }
+ }
+}
+
static void
ironlake_dump_regs(void)
{
intel_check_pch();
ironlake_dump_regs();
}
- else
+ else if (IS_945GM(devid)) {
+ i945_dump_mi_regs();
+ intel_dump_regs();
+ } else
intel_dump_regs();
return 0;