AC_DEFINE(HAVE_CPU_SPARC, 1, [Define if the target CPU is a PPC]) ;;
xmips*) HAVE_CPU_MIPS=yes
AC_DEFINE(HAVE_CPU_MIPS, 1, [Define if the target CPU is a MIPS]) ;;
+ xhppa*) HAVE_CPU_HPPA=yes
+ AC_DEFINE(HAVE_CPU_HPPA, 1, [Define if the target CPU is a HPPA]) ;;
esac
dnl Determine endianness
+/***** HP-PA *****/
+#elif defined(HAVE_CPU_HPPA)
+
+#define GST_ARCH_SET_SP(stackpointer) \
+ __asm__("copy %0,%%sp\n\t" : : "r"(stackpointer));
+
+#define GST_ARCH_CALL(target) \
+ __asm__("copy $1,%%r22\n\t" // set call address \
+ ".CALL\n\t" // call pseudo insn (why?) \
+ "bl $$dyncall,%%r31\n\t" : : "r"(target));
+
+// assume stackframe is 16 bytes
+#define GST_ARCH_SETUP_STACK(sp) sp -= 4
+
+
+
#else
#error Need to know about this architecture, or have a generic implementation
#endif