// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Cadence SPI controller driver (master mode only)
+ * Cadence SPI controller driver (master and slave mode)
*
* Copyright (C) 2008 - 2014 Xilinx, Inc.
*
/**
* cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
* @xspi: Pointer to the cdns_spi structure
+ * @is_slave: Flag to indicate slave or master mode
+ * * On reset the SPI controller is configured to slave or master mode.
+ * In master mode baud rate divisor is set to 4, threshold value for TX FIFO
+ * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
*
- * On reset the SPI controller is configured to be in master mode, baud rate
- * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
- * to 1 and size of the word to be transferred as 8 bit.
* This function initializes the SPI controller to disable and clear all the
* interrupts, enable manual slave select and manual start, deselect all the
* chip select lines, and enable the SPI controller.
*/
-static void cdns_spi_init_hw(struct cdns_spi *xspi)
+static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_slave)
{
- u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
+ u32 ctrl_reg = 0;
+
+ if (!is_slave)
+ ctrl_reg |= CDNS_SPI_CR_DEFAULT;
if (xspi->is_decoded_cs)
ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
}
/**
+ * cdns_spi_read_rx_fifo - Reads the RX FIFO with as many bytes as possible
+ * @xspi: Pointer to the cdns_spi structure
+ * @count: Read byte count
+ */
+static void cdns_spi_read_rx_fifo(struct cdns_spi *xspi, unsigned long count)
+{
+ u8 data;
+
+ /* Read out the data from the RX FIFO */
+ while (count > 0) {
+ data = cdns_spi_read(xspi, CDNS_SPI_RXD);
+ if (xspi->rxbuf)
+ *xspi->rxbuf++ = data;
+ xspi->rx_bytes--;
+ count--;
+ }
+}
+
+/**
* cdns_spi_irq - Interrupt service routine of the SPI controller
* @irq: IRQ number
* @dev_id: Pointer to the xspi structure
spi_finalize_current_transfer(ctlr);
status = IRQ_HANDLED;
} else if (intr_status & CDNS_SPI_IXR_TXOW) {
- unsigned long trans_cnt;
-
- trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
+ int trans_cnt = cdns_spi_read(xspi, CDNS_SPI_THLD);
+ /* Set threshold to one if number of pending are
+ * less than half fifo
+ */
+ if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
+ cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
- /* Read out the data from the RX FIFO */
while (trans_cnt) {
- u8 data;
-
- data = cdns_spi_read(xspi, CDNS_SPI_RXD);
- if (xspi->rxbuf)
- *xspi->rxbuf++ = data;
-
- xspi->rx_bytes--;
+ cdns_spi_read_rx_fifo(xspi, 1);
+
+ if (xspi->tx_bytes) {
+ if (xspi->txbuf)
+ cdns_spi_write(xspi, CDNS_SPI_TXD,
+ *xspi->txbuf++);
+ else
+ cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
+ xspi->tx_bytes--;
+ }
trans_cnt--;
}
-
- if (xspi->tx_bytes) {
- /* There is more data to send */
- cdns_spi_fill_tx_fifo(xspi);
- } else {
- /* Transfer is completed */
+ if (!xspi->tx_bytes) {
+ /* Fixed delay due to controller limitation with
+ * RX_NEMPTY incorrect status
+ * Xilinx AR:65885 contains more details
+ */
+ udelay(10);
+ cdns_spi_read_rx_fifo(xspi, xspi->rx_bytes);
cdns_spi_write(xspi, CDNS_SPI_IDR,
CDNS_SPI_IXR_DEFAULT);
spi_finalize_current_transfer(ctlr);
static int cdns_prepare_message(struct spi_controller *ctlr,
struct spi_message *msg)
{
- cdns_spi_config_clock_mode(msg->spi);
+ if (!spi_controller_is_slave(ctlr))
+ cdns_spi_config_clock_mode(msg->spi);
return 0;
}
* @transfer: Pointer to the spi_transfer structure which provides
* information about next transfer parameters
*
- * This function fills the TX FIFO, starts the SPI transfer and
+ * This function in master mode fills the TX FIFO, starts the SPI transfer and
* returns a positive transfer count so that core will wait for completion.
+ * This function in slave mode fills the TX FIFO and wait for transfer trigger.
*
* Return: Number of bytes transferred in the last transfer
*/
xspi->tx_bytes = transfer->len;
xspi->rx_bytes = transfer->len;
- cdns_spi_setup_transfer(spi, transfer);
+ if (!spi_controller_is_slave(ctlr))
+ cdns_spi_setup_transfer(spi, transfer);
+
+ /* Set TX empty threshold to half of FIFO depth
+ * only if TX bytes are more than half FIFO depth.
+ */
+ if (xspi->tx_bytes > (xspi->tx_fifo_depth >> 1))
+ cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
+
cdns_spi_fill_tx_fifo(xspi);
spi_transfer_delay_exec(transfer);
* information about the controller.
*
* This function disables the SPI master controller when no slave selected.
+ * This function flush out if any pending data in FIFO.
*
* Return: 0 always
*/
{
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
u32 ctrl_reg;
+ unsigned int cnt = xspi->tx_fifo_depth;
+
+ if (spi_controller_is_slave(ctlr)) {
+ while (cnt--)
+ cdns_spi_read(xspi, CDNS_SPI_RXD);
+ }
/* Disable the SPI if slave is deselected */
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
- if (ctrl_reg == CDNS_SPI_NOSS)
+ if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_slave(ctlr))
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
+ /* Reset to default */
+ cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
return 0;
}
}
/**
+ * cdns_slave_abort - Abort slave transfer
+ * @ctlr: Pointer to the spi_controller structure
+ *
+ * This function abort slave transfer if there any transfer timeout.
+ *
+ * Return: 0 always
+ */
+static int cdns_slave_abort(struct spi_controller *ctlr)
+{
+ struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
+ u32 intr_status;
+
+ intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
+ cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
+ cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
+ spi_finalize_current_transfer(ctlr);
+
+ return 0;
+}
+
+/**
* cdns_spi_probe - Probe method for the SPI driver
* @pdev: Pointer to the platform_device structure
*
struct spi_controller *ctlr;
struct cdns_spi *xspi;
u32 num_cs;
+ bool slave;
+
+ slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
+ if (slave)
+ ctlr = spi_alloc_slave(&pdev->dev, sizeof(*xspi));
+ else
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
- ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
if (!ctlr)
return -ENOMEM;
goto remove_ctlr;
}
- xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
- if (IS_ERR(xspi->ref_clk)) {
- dev_err(&pdev->dev, "ref_clk clock not found.\n");
- ret = PTR_ERR(xspi->ref_clk);
- goto remove_ctlr;
- }
-
ret = clk_prepare_enable(xspi->pclk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
goto remove_ctlr;
}
- ret = clk_prepare_enable(xspi->ref_clk);
- if (ret) {
- dev_err(&pdev->dev, "Unable to enable device clock.\n");
- goto clk_dis_apb;
- }
+ if (!spi_controller_is_slave(ctlr)) {
+ xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
+ if (IS_ERR(xspi->ref_clk)) {
+ dev_err(&pdev->dev, "ref_clk clock not found.\n");
+ ret = PTR_ERR(xspi->ref_clk);
+ goto clk_dis_apb;
+ }
- pm_runtime_use_autosuspend(&pdev->dev);
- pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
- pm_runtime_get_noresume(&pdev->dev);
- pm_runtime_set_active(&pdev->dev);
- pm_runtime_enable(&pdev->dev);
+ ret = clk_prepare_enable(xspi->ref_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to enable device clock.\n");
+ goto clk_dis_apb;
+ }
- ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
- if (ret < 0)
- ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
- else
- ctlr->num_chipselect = num_cs;
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
+ pm_runtime_get_noresume(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
- ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
- &xspi->is_decoded_cs);
- if (ret < 0)
- xspi->is_decoded_cs = 0;
+ ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
+ if (ret < 0)
+ ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
+ else
+ ctlr->num_chipselect = num_cs;
+
+ ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
+ &xspi->is_decoded_cs);
+ if (ret < 0)
+ xspi->is_decoded_cs = 0;
+ }
cdns_spi_detect_fifo_depth(xspi);
/* SPI controller initializations */
- cdns_spi_init_hw(xspi);
+ cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
ctlr->prepare_message = cdns_prepare_message;
ctlr->transfer_one = cdns_transfer_one;
ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
- ctlr->set_cs = cdns_spi_chipselect;
- ctlr->auto_runtime_pm = true;
- ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
-
- xspi->clk_rate = clk_get_rate(xspi->ref_clk);
- /* Set to default valid value */
- ctlr->max_speed_hz = xspi->clk_rate / 4;
- xspi->speed_hz = ctlr->max_speed_hz;
-
+ ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
- pm_runtime_mark_last_busy(&pdev->dev);
- pm_runtime_put_autosuspend(&pdev->dev);
-
+ if (!spi_controller_is_slave(ctlr)) {
+ ctlr->mode_bits |= SPI_CS_HIGH;
+ ctlr->set_cs = cdns_spi_chipselect;
+ ctlr->auto_runtime_pm = true;
+ xspi->clk_rate = clk_get_rate(xspi->ref_clk);
+ /* Set to default valid value */
+ ctlr->max_speed_hz = xspi->clk_rate / 4;
+ xspi->speed_hz = ctlr->max_speed_hz;
+ pm_runtime_mark_last_busy(&pdev->dev);
+ pm_runtime_put_autosuspend(&pdev->dev);
+ } else {
+ ctlr->mode_bits |= SPI_NO_CS;
+ ctlr->slave_abort = cdns_slave_abort;
+ }
ret = spi_register_controller(ctlr);
if (ret) {
dev_err(&pdev->dev, "spi_register_controller failed\n");
return ret;
clk_dis_all:
- pm_runtime_set_suspended(&pdev->dev);
- pm_runtime_disable(&pdev->dev);
- clk_disable_unprepare(xspi->ref_clk);
+ if (!spi_controller_is_slave(ctlr)) {
+ pm_runtime_set_suspended(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ clk_disable_unprepare(xspi->ref_clk);
+ }
clk_dis_apb:
clk_disable_unprepare(xspi->pclk);
remove_ctlr:
struct spi_controller *ctlr = dev_get_drvdata(dev);
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
- cdns_spi_init_hw(xspi);
+ cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
return spi_controller_resume(ctlr);
}
projects / platform / kernel / linux-starfive.git / commitdiff