--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Verify that we can fold shifts into G_ICMP variants.
+#
+# Because these are selected as a SUBS, we can fold a shift into the addressing
+# mode in the same way.
+#
+# We should not have shifts in any of the compares below. These should be
+# folded into the SUBSWrs instruction.
+
+...
+---
+name: eq_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: eq_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: eq_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: eq_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: eq_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: eq_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: ne_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ne_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: ne_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ne_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: ne_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ne_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: ult_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ult_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ult_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ult_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ult_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ult_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ugt_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ugt_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ugt_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ugt_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ugt_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ugt_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+
+...
+---
+name: uge_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: uge_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: uge_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: uge_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: uge_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: uge_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+
+...
+---
+name: ule_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ule_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ule_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ule_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: ule_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: ule_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+...
+---
+name: slt_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: slt_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: slt_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: slt_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: slt_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: slt_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sgt_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sgt_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sgt_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sgt_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sgt_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sgt_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sge_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sge_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sge_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sge_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sge_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sge_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+
+...
+---
+name: sle_shl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sle_shl
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_SHL %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sle_ashr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sle_ashr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...
+---
+name: sle_lshr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sle_lshr
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy0:gpr32 = COPY $w0
+ ; CHECK: %copy1:gpr32 = COPY $w1
+ ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+ ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; CHECK: $w0 = COPY %cmp
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy0:gpr(s32) = COPY $w0
+ %copy1:gpr(s32) = COPY $w1
+ %three:gpr(s32) = G_CONSTANT i32 3
+ %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
+ %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
+ $w0 = COPY %cmp(s32)
+ RET_ReallyLR implicit $w0
+...